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https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-03-22 05:00:29 +08:00
CHG: "hf legic sim" old imp, uses two timers, we have one. I'm seriously starting on thinking about a UART instead, to read the dmabuffer. If only I knew howto.
This commit is contained in:
iceman1001
parent
4697964f6a
commit
f8ff1483eb
1 changed files with 72 additions and 29 deletions
101
armsrc/legicrf.c
101
armsrc/legicrf.c
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@ -69,7 +69,7 @@ static void setup_timer(void) {
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*/
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// At TIMER_CLOCK3 (MCK/32)
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// testing calculating in (us) microseconds.
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// testing calculating in ticks. 1.5ticks = 1us
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#define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
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#define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
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#define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
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@ -297,19 +297,18 @@ static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
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// Setup pm3 as a Legic Reader
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static uint32_t setup_phase_reader(uint8_t iv) {
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// Switch on carrier and let the tag charge for 1ms
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// Switch on carrier and let the tag charge for 5ms
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HIGH(GPIO_SSC_DOUT);
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WaitUS(5000);
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WaitUS(5000);
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ResetTicks();
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// no keystream yet
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legic_prng_init(0);
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// send IV handshake
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frame_sendAsReader(iv, 7);
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// Now both tag and reader has same IV. Prng can start.
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// tag and reader has same IV.
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legic_prng_init(iv);
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frame_receiveAsReader(¤t_frame, 6);
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@ -655,7 +654,7 @@ static void frame_handle_tag(struct legic_frame const * const f)
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// log
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//uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
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//LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
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Dbprintf("ICE: enter frame_handle_tag: %02x ", f->bits);
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//Dbprintf("ICE: enter frame_handle_tag: %02x ", f->bits);
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/* First Part of Handshake (IV) */
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if(f->bits == 7) {
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@ -694,9 +693,7 @@ static void frame_handle_tag(struct legic_frame const * const f)
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if((f->bits == 6) && (f->data == xored)) {
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legic_state = STATE_CON;
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//ResetTimer(timer);
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//WaitUS(200);
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ResetTimer(timer);
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WaitTicks(300);
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return;
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@ -765,7 +762,6 @@ static void frame_handle_tag(struct legic_frame const * const f)
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*/
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static void emit(int bit) {
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Dbprintf("ICE: enter emit:");
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switch (bit) {
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case 1:
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frame_append_bit(¤t_frame, 1);
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@ -799,22 +795,35 @@ void LegicRfSimulate(int phase, int frame, int reqresp)
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*/
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int old_level = 0, active = 0;
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volatile uint32_t level = 0;
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volatile int32_t level = 0;
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legic_state = STATE_DISCON;
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legic_phase_drift = phase;
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legic_frame_drift = frame;
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legic_reqresp_drift = reqresp;
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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/* to get the stream of bits from FPGA in sim mode.*/
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaSetupSsc();
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
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/* to get the stream of bits from FPGA in sim mode.*/
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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// Set up the synchronous serial port
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//FpgaSetupSsc();
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// connect Demodulated Signal to ADC:
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
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#define LEGIC_DMA_BUFFER 256
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// The DMA buffer, used to stream samples from the FPGA
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//uint8_t *dmaBuf = BigBuf_malloc(LEGIC_DMA_BUFFER);
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//uint8_t *data = dmaBuf;
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// Setup and start DMA.
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// if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER) ){
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// if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
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// return;
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// }
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//StartCountSspClk();
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/* Bitbang the receiver */
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// LINE_IN;
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AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
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@ -832,7 +841,38 @@ void LegicRfSimulate(int phase, int frame, int reqresp)
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LED_B_ON();
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DbpString("Starting Legic emulator, press button to end");
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/*
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* The mode FPGA_HF_SIMULATOR_MODULATE_212K works like this.
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* - A 1-bit input to the FPGA becomes 8 pulses on 212kHz (fc/64) (18.88us).
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* - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
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*
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* In this mode the SOF can be written as 00011101 = 0x1D
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* The EOF can be written as 10111000 = 0xb8
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* A logic 1 is 01
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* A logic 0 is 10
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volatile uint8_t b;
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uint8_t i = 0;
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while( !BUTTON_PRESS() ) {
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WDT_HIT();
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// not sending anything.
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if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
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AT91C_BASE_SSC->SSC_THR = 0x00;
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}
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// receive
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if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) {
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b = (uint8_t) AT91C_BASE_SSC->SSC_RHR;
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bd[i] = b;
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++i;
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// if(OutOfNDecoding(b & 0x0f))
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// *len = Uart.byteCnt;
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}
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}
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*/
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while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
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level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
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@ -840,23 +880,23 @@ void LegicRfSimulate(int phase, int frame, int reqresp)
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uint32_t time = GET_TICKS;
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if (level != old_level) {
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if (level) {
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if (level == 1) {
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ResetTicks();
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//Dbprintf("start, %u ", time);
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StartTicks();
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// did we get a signal
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if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
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/* 1 bit */
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// 1 bit
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emit(1);
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active = 1;
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LED_A_ON();
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} else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
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/* 0 bit */
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// 0 bit
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emit(0);
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active = 1;
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LED_A_ON();
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} else if (active) {
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/* invalid */
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// invalid
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emit(-1);
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active = 0;
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LED_A_OFF();
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@ -864,6 +904,7 @@ void LegicRfSimulate(int phase, int frame, int reqresp)
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}
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}
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/* Frame end */
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if(time >= (RWD_TIME_1 + RWD_TIME_FUZZ) && active) {
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emit(-1);
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@ -877,20 +918,22 @@ void LegicRfSimulate(int phase, int frame, int reqresp)
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* side-effect of clearing any pending state in there.
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*/
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//if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
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//if(time >= (20 * RWD_TIME_1) )
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//StopTicks();
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if(time >= (20 * RWD_TIME_1) )
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StopTicks();
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old_level = level;
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WDT_HIT();
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}
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}
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WDT_HIT();
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DbpString("LEGIC Prime emulator stopped");
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switch_off_tag_rwd();
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FpgaDisableSscDma();
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LEDsoff();
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cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
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}
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//-----------------------------------------------------------------------------
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// Code up a string of octets at layer 2 (including CRC, we don't generate
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// that here) so that they can be transmitted to the reader. Doesn't transmit
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