From ff5b04690351ba04f3a15a0b725fbc41bc638ed0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Dr=C3=B6scher?= <github@anticat.ch>
Date: Wed, 8 Aug 2018 00:11:14 +0200
Subject: [PATCH] change: re-added status LEDs

- LED_A: FPGA and 13.56MHz carrier is active
- LED_B: Reading Byte
- LED_C: Writing Byte
---
 armsrc/legicrf.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/armsrc/legicrf.c b/armsrc/legicrf.c
index 19ea87bd2..f2e80eee2 100644
--- a/armsrc/legicrf.c
+++ b/armsrc/legicrf.c
@@ -97,6 +97,7 @@ static inline int32_t sample_power() {
 // has a delay loop that aligns rx_bit calls to the TAG tx timeslots.
 static inline bool rx_bit() {
   static int32_t p[5];
+
   for(size_t i = 0; i<5; ++i) {
     p[i] = sample_power();
   }
@@ -254,6 +255,7 @@ static void init_reader(bool clear_mem) {
                   | FPGA_HF_READER_RX_XCORR_848_KHZ
                   | FPGA_HF_READER_RX_XCORR_QUARTER);
   SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
+  LED_A_ON();
 
   // configure SSC with defaults
   FpgaSetupSsc();
@@ -338,10 +340,12 @@ static int16_t read_byte(uint16_t index, uint8_t cmd_sz) {
   uint16_t cmd = (index << 1) | LEGIC_READ;
 
   // read one byte
+  LED_B_ON();
   legic_prng_forward(2);
   tx_frame(cmd, cmd_sz);
   legic_prng_forward(2);
   uint32_t frame = rx_frame(12);
+  LED_B_OFF();
 
   // split frame into data and crc
   uint8_t byte = BYTEx(frame, 0);
@@ -368,9 +372,11 @@ bool write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
   cmd |= (crc & 0xF) << (addr_sz + 1 + 8);          // and crc
 
   // send write command
+  LED_C_ON();
   legic_prng_forward(2);
   tx_frame(cmd, addr_sz + 1 + 8 + 4); // cmd_sz = addr_sz + cmd + data + crc
   legic_prng_forward(3);
+  LED_C_OFF();
 
   // wait for ack
   return rx_ack();