iceman1001
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85aac72855
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new fpga images
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2023-08-29 16:46:52 +02:00 |
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iceman1001
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ba320f26f7
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ensure registers and vars is set correct
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2023-08-28 15:34:36 +02:00 |
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iceman1001
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114dda1582
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After testing and verification its found that the SHALLOW MODULATION in HF is not working well in RDV4. Swapping from PWR_OE4 to PWR_OE1 makes it much better. Thanks to @d18c7db for solution and @gentlekiwi for testing and never giving up on finding the bug
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2023-08-28 12:00:44 +02:00 |
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iceman1001
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71023d0c6e
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regenerated with the HF update
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2023-07-12 16:25:14 +02:00 |
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d18c7db
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c59bdec4f2
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Unified fpga folders
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2023-05-30 19:47:27 +02:00 |
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