Commit graph

1098 commits

Author SHA1 Message Date
iceman1001 1709c1ce1a chg: flash_mem - hooked up client - device comms 2018-02-13 15:36:20 +01:00
iceman1001 0495e93b6d add: flash memory support 2018-02-13 14:12:28 +01:00
iceman1001 ad73af95c2 ADD: beginning to add SPI to access flash memory. 2018-02-13 11:41:23 +01:00
iceman1001 85b2533435 chg: 'hw tune' device side should be unsigned and only 1024 (10b ADC) 2018-02-13 11:40:05 +01:00
iceman1001 dc66765306 chg: 'lf cmdread' - adjusting loop 2018-02-09 00:27:02 +01:00
iceman1001 5adb9af78f chg: 'hw tune' - compensating the 3% error marginal. 2018-02-09 00:25:45 +01:00
iceman1001 fe34cac012 FIX: 'hf mf darkside' - no more WDT crashes. plus positive sideeffects (@pwpiwi)
https://github.com/Proxmark/proxmark3/pull/569
2018-02-08 19:11:35 +01:00
iceman1001 de631c32ac textual 2018-02-08 10:31:23 +01:00
iceman1001 ff07af84bf fix: StandAloneMode samyrun, proxbrute, - id values are unsigned 2018-02-08 09:55:23 +01:00
iceman1001 374571046d remove debug.. 2018-02-07 20:12:16 +01:00
iceman1001 aee5fcb24a debugs 2018-02-07 17:22:23 +01:00
iceman1001 094b5db9c5 fix: configure mux at startup 2018-02-07 17:21:51 +01:00
iceman1001 a2ac368fdb fix.. wrong switch 2018-02-07 13:14:04 +01:00
iceman1001 75d04307a1 chg: adapting some HF voltage readings. 2018-02-07 13:11:10 +01:00
iceman1001 3d2fd2e3a1 FIX: start up,MUXSEL_HIPKD(PA19),MUXSEL_LOPKD(PA20) are floating state. Should adapt FPGA image aswell. 2018-02-07 12:08:50 +01:00
iceman1001 13bb29a386 fix: 'hf mf fchk' - releasing memory when finished is a good thing 2018-02-05 22:59:49 +01:00
iceman1001 3464fbe1df fix 'hf mf darkside' - adapted solution from @pwpivi 2018-02-05 20:46:14 +01:00
iceman1001 fca1c9b7cf chg: 'hf mf mifare' - (deviceside) reset cycles when negative or too large 2018-02-05 16:47:10 +01:00
Jean-Pierre Clair 847656c613 spelling error authetication instead of authentication 2018-02-05 14:09:38 +01:00
iceman1001 6605d92fbb chg: tried making the reselect more stable.
chg: 'hf iclass readblk'
chg: 'hf iclass writeblk'
chg: 'hf iclass dump'
chg: 'hf iclass clone'
        all commands now has 'v'  verbose parameter for more detailed output.
2018-02-04 12:25:55 +01:00
iceman1001 6a9ddf6e69 chg 'hf iclass chk' - increased timeout, switch off antenna before each run in order to reset card, three retires. all this make it more stable. 2018-02-04 10:20:38 +01:00
iceman1001 dc25f9212f FIX: 'hf iclass sim 2'
FIX: 'hf iclass sim 4'
FIX: 'hf iclass loclass' - this fixes the bug where loclass assumes the epurse value is all zeros, while it now should save the epurse value during the simulation if it is updated/read.

I assume a empty valid epurse, while an all zero epurse is too much easy to detect as a anomaly.
2018-02-04 00:52:29 +01:00
iceman1001 856e2770a6 chg: 'hf iclass sim' different output 2018-02-01 17:44:27 +01:00
iceman1001 e0373212a3 chg: 'hf iclass sim' - sim2, 4 get less default output, set DBG 4 for verbose 2018-02-01 16:10:24 +01:00
iceman1001 fa5b550fa8 chg: should be a define. 2018-02-01 15:35:00 +01:00
iceman1001 145bccdea8 chg: wrong type 2018-02-01 15:33:10 +01:00
iceman1001 519cc72966 chg: crc change 2018-02-01 15:22:01 +01:00
iceman1001 52d69ed4ee CHG: refactor CRC16 algos. This is a big change, most likely some parts broke, hard to test it all. 2018-02-01 15:19:47 +01:00
iceman1001 721ba5d287 fix: 'hf iclass sim' - too small buffers caused sim to fail 2018-02-01 09:31:30 +01:00
iceman1001 c6207d09e1 chg: 'hf felica reader' is better, almost working good 2018-01-30 03:29:37 +01:00
iceman1001 50743b7e88 rem: 'hf iclass' blocknum LUT is gone. Removed also functionality for it. 2018-01-29 16:44:49 +01:00
iceman1001 5c380767e8 chg: 'hf iclass' removed a blocknum LUT implementation. My guess is the new crc16_iclass will do fine. 2018-01-29 16:38:03 +01:00
iceman1001 b39332e938 REM: 'hf 15 debug' removed command, unified with mf_debuglevel instead. The idea is to have ONE debug flag on deviceside. 2018-01-29 15:58:00 +01:00
iceman1001 787d87e0e6 testing to make dma buffer larger. 2018-01-29 13:42:42 +01:00
iceman1001 c04ac4f9ac ADD: 'hf felica reader' - added pm3 as FeliCa reader
ADD:  raw commands -  added the basis for sending RAW commands to FeliCa.
CHG: CRC16 rework,  uses table based implementation.  This will change more functions as I go on.
2018-01-29 13:42:02 +01:00
iceman1001 fd854a9308 chg: added Abrasive's uart implementation, its simpler to understand but the downside it doesn't do both speeds. (1/4 , 1/2556).
ref 2b8bff7dae
2018-01-28 12:36:41 +01:00
iceman1001 57df6a1a7e revert: add reflect function since its used in crc.c 2018-01-28 10:49:57 +01:00
iceman1001 cf44d04be1 add: reflect16
rem:  swapbits, reflect
2018-01-28 10:46:46 +01:00
iceman1001 e76b4f93b8 notes 2018-01-27 23:15:08 +01:00
iceman1001 ede55a1498 add: fast 8bit reversal. 2018-01-27 22:20:56 +01:00
iceman1001 60afef3938 FIX: 'hf snoop' - forcing function to clean up AT91C_BASE_SSC->SSC_RFMR into default setup values.
FIX: 'lf ti' - forcing to cleaning up of SSC when finished.
2018-01-27 20:30:50 +01:00
iceman1001 a6c50d7de2 chg: 'hf 14b' removed a delay loop when transmit as reader 2018-01-25 18:44:25 +01:00
iceman1001 5939164635 FIX: 'hf 15' timouts bugs when wait is set == 0...
thanks @lnv42  for fix  84cb4f6bbf
2018-01-21 18:34:29 +01:00
iceman1001 be82f9f018 DEL: 'hf mf sniff' - since it is very similar to 'hf 14a sniff' , I removed this command. The desired functionality will become a new 'hf list mf' option in the future. 2018-01-18 14:11:22 +01:00
iceman1001 b4afc8cdc4 fix: 'hf mf sniff' - @merlokk 's adjustments 2018-01-17 00:28:40 +01:00
iceman1001 de983252eb chg: dma macros instead 2018-01-17 00:27:13 +01:00
iceman1001 93ecfddb88 CHG: iso15 from b8f35947f2 @lnv42 2018-01-16 21:07:58 +01:00
iceman1001 466bbe1733 fix: 'hf mf hardnested' - too fast timeouts. https://github.com/Proxmark/proxmark3/issues/518 2018-01-15 14:22:46 +01:00
iceman1001 5ee4eeb84b chg: 'hf mf sim' wrong debuglevel for message 2018-01-11 22:08:02 +01:00
iceman1001 5ea8f73547 FIX: cmd_send has wrong varible definitions, leading to loss of values. 2018-01-11 21:47:27 +01:00