Commit graph

30 commits

Author SHA1 Message Date
iceman1001 5abae85eda legic sim should work now.... 2023-09-07 12:54:46 +02:00
iceman1001 d9f2d5287e maybe the return codes are wrong in legic sim now 2023-07-27 16:46:52 +02:00
iceman1001 96944aec69 reinstate less checks of data_available 2023-07-27 12:37:42 +02:00
iceman1001 c70e5beeac changed legic sim to have a different loop and exit message. Added some colors in output and the return codes on deviceside for legisim now uses the same PM3_E* styled 2023-07-17 19:31:37 +02:00
Philippe Teuwen b703bb746b Adapting license headers, WIP 2022-01-06 02:20:38 +01:00
Philippe Teuwen 88308ea727 typos 2021-10-10 01:35:45 +02:00
Philippe Teuwen 5b54385347 rename globals 2021-08-21 23:08:26 +02:00
iceman1001 edebf17be5 keep WDT happy 2020-09-15 17:26:24 +02:00
iceman1001 0be35a8e7e style 2020-09-07 10:35:09 +02:00
iceman1001 718e6d2ce8 hf legic sim -> text, use NG, report back 2020-09-06 21:41:04 +02:00
iceman1001 837efdf5c4 chg: adapt to fpga changes 2020-07-02 12:36:24 +02:00
iceman1001 47634f5550 change: remove inline directive in armsrc, since we are optimizing for size 2020-05-19 17:15:07 +02:00
Philippe Teuwen 026707b960 arm: fix prototypes 2020-05-11 13:48:57 +02:00
Philippe Teuwen 838d345918 resolve inline warnings 2020-05-11 13:48:57 +02:00
Philippe Teuwen 8bdda55115 Fix prompt colors in log -> spurious space in color macros -> adjust lots of files... 2020-04-22 02:22:55 +02:00
iceman1001 c8b51ccf25 chg: legic standalone - now saves read cards to flashmemory (RDV4)\n also simulates correct cardtype.\n It goes direct into recording / reading a tag. Once a complete dump is done, it starts to simulate 2020-03-30 15:11:48 +02:00
Philippe Teuwen 129b1c4b1f make sure all .c include their own .h 2019-10-26 18:56:36 +02:00
Philippe Teuwen d19754567d summer restructuring:
* .h include only the strict minimum for their own parsing
  * this forces all files to include explicitment their needs and not count on far streched dependencies
  * this helps Makefile to rebuild only the minimum
  * according to this rule, most standalone .h are now gone
  * big app.h is gone
  * remove seldom __cplusplus, if c++ happens, everything will have to be done properly anyway
* all unrequired include were removed
* split common/ into common/ (client+arm) and common_arm/ (os+bootloader)
  * bring zlib to common/
  * bring stuff not really/not yet used in common back to armsrc/ or client/
  * bring liblua into client/
  * bring uart into client/
  * move some portions of code around (dbprint, protocols,...)
* rename unused files into *_disabled.[ch] to make it explicit
* rename soft Uarts between 14a, 14b and iclass, so a standalone could use several without clash
* remove PrintAndLogDevice
* move deprecated-hid-flasher from client to tools
* Makefiles
  * treat deps in armsrc/ as in client/
  * client: stop on warning (-Werror), same as for armsrc/

Tested on:

* all standalone modes
* Linux
2019-08-11 21:42:01 +02:00
Philippe Teuwen 3b12ba2e93 replace usb_poll_validate_length() by data_available() that supports USART too 2019-06-03 00:01:08 +02:00
Philippe Teuwen 961d929f4d changing {} style to match majority of previous style 2019-03-10 11:20:22 +01:00
Philippe Teuwen 0373696662 make style 2019-03-10 00:00:59 +01:00
iceman1001 730a7e8044 FIX: 'hf legic sim' - needed even more timeout.
see https://github.com/RfidResearchGroup/proxmark3/issues/83
2019-01-25 13:48:53 +01:00
iceman1001 803aab7431 FIX: 'hf legic sim' - longer timeout for writes? (@drandreas)
see https://github.com/RfidResearchGroup/proxmark3/issues/83
2019-01-25 11:58:00 +01:00
Chris ba9de80eeb chg: 'hf legic sim' break sim by sending another cmd 2018-09-09 11:29:11 +02:00
AntiCat e1fa1e659a Legic: Implemented write command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 2981fe7ce8 Legic: Implemented read command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat cd78b00815 Legic: Implemented setup phase for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 2c6c4e5bc6 Legic: Implemented trace log 2018-09-05 23:03:05 +02:00
AntiCat fe91a3f52f Legic: Implemented RX and TX for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 61e4eac2b2 Legic: Moved card simulator into separate file & cleaned interface.
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
2018-09-05 23:03:04 +02:00