Commit graph

16 commits

Author SHA1 Message Date
Philippe Teuwen b703bb746b Adapting license headers, WIP 2022-01-06 02:20:38 +01:00
Philippe Teuwen 55fa5e7c35 make style 2020-10-11 22:40:05 +02:00
iceman1001 0c54d13c47 added a precision timer ( 0.6ns for 43ms) 2020-10-09 14:30:34 +02:00
Philippe Teuwen 026707b960 arm: fix prototypes 2020-05-11 13:48:57 +02:00
Philippe Teuwen 98d641dba5 WaitUS/WaitMS: accept uint32_t 2019-10-09 12:06:45 +02:00
iceman1001 ff66ea896b ssp clock delta 2019-09-11 15:16:20 +02:00
Philippe Teuwen d19754567d summer restructuring:
* .h include only the strict minimum for their own parsing
  * this forces all files to include explicitment their needs and not count on far streched dependencies
  * this helps Makefile to rebuild only the minimum
  * according to this rule, most standalone .h are now gone
  * big app.h is gone
  * remove seldom __cplusplus, if c++ happens, everything will have to be done properly anyway
* all unrequired include were removed
* split common/ into common/ (client+arm) and common_arm/ (os+bootloader)
  * bring zlib to common/
  * bring stuff not really/not yet used in common back to armsrc/ or client/
  * bring liblua into client/
  * bring uart into client/
  * move some portions of code around (dbprint, protocols,...)
* rename unused files into *_disabled.[ch] to make it explicit
* rename soft Uarts between 14a, 14b and iclass, so a standalone could use several without clash
* remove PrintAndLogDevice
* move deprecated-hid-flasher from client to tools
* Makefiles
  * treat deps in armsrc/ as in client/
  * client: stop on warning (-Werror), same as for armsrc/

Tested on:

* all standalone modes
* Linux
2019-08-11 21:42:01 +02:00
Philippe Teuwen e0c9e2b0d1 rework usart RX timings 2019-05-22 23:30:52 +02:00
Philippe Teuwen 26eb54b965 style 2019-04-06 01:00:54 +02:00
Philippe Teuwen 1b2601a48a Add missing EOF LF 2019-03-12 00:12:26 +01:00
Chris 5f77121694 initial commit to be in sync the-soon-defunct repo pm3rdv40. 2018-08-12 21:54:31 +02:00
Andreas Dröscher 9d330dde87 fix: 32bit tick timer based on TC0 and TC1
TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.

SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.

The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
2018-08-12 12:41:11 +02:00
iceman1001 d41efbf21b ADD: added a StopTicks functions, to disable the timer used for ticks (TC0, TC1) 2016-10-07 00:13:09 +02:00
iceman1001 c649c43389 CHG: finally, the ticks timer does what it is supposed to do. 32bits and working. 2016-09-29 21:36:43 +02:00
iceman1001 fabef615ec CHG: added addresize to legic select struct.
CHG: TIMER, it turns out the TC0, TC1 and TC2 is only 16bit.  So adjust to use two clocks to get a 32bit timer.
CHG: code clean up in legic device side.  consistency with variable names..
2016-09-29 17:43:39 +02:00
iceman1001 22f4dca88c CHG: extracted some timers functionality, to get unified access to a timer/clock which counts in ticks. Moved stuff from util.c 2016-09-21 19:03:32 +02:00