RfidResearchGroup/proxmark3
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5351 commits 3 branches 14 tags 87 MiB
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11 commits

Author SHA1 Message Date
Philippe Teuwen
961d929f4d changing {} style to match majority of previous style 2019-03-10 11:20:22 +01:00
Philippe Teuwen
0373696662 make style 2019-03-10 00:00:59 +01:00
iceman1001
730a7e8044 FIX: 'hf legic sim' - needed even more timeout. 
see https://github.com/RfidResearchGroup/proxmark3/issues/83
 2019-01-25 13:48:53 +01:00
iceman1001
803aab7431 FIX: 'hf legic sim' - longer timeout for writes? (@drandreas) 
see https://github.com/RfidResearchGroup/proxmark3/issues/83
 2019-01-25 11:58:00 +01:00
Chris
ba9de80eeb chg: 'hf legic sim' break sim by sending another cmd 2018-09-09 11:29:11 +02:00
AntiCat
e1fa1e659a Legic: Implemented write command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat
2981fe7ce8 Legic: Implemented read command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat
cd78b00815 Legic: Implemented setup phase for card simulation 2018-09-05 23:03:05 +02:00
AntiCat
2c6c4e5bc6 Legic: Implemented trace log 2018-09-05 23:03:05 +02:00
AntiCat
fe91a3f52f Legic: Implemented RX and TX for card simulation 2018-09-05 23:03:05 +02:00
AntiCat
61e4eac2b2 Legic: Moved card simulator into separate file & cleaned interface. 
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
 2018-09-05 23:03:04 +02:00