6 commits

Author	SHA1	Message	Date
iceman1001	e4835e69a3	recompiled the fpga images	2024-01-24 17:06:41 +01:00
iceman1001	85aac72855	new fpga images	2023-08-29 16:46:52 +02:00
iceman1001	ba320f26f7	ensure registers and vars is set correct	2023-08-28 15:34:36 +02:00
iceman1001	114dda1582	After testing and verification its found that the SHALLOW MODULATION in HF is not working well in RDV4. Swapping from PWR_OE4 to PWR_OE1 makes it much better. Thanks to @d18c7db for solution and @gentlekiwi for testing and never giving up on finding the bug	2023-08-28 12:00:44 +02:00
iceman1001	71023d0c6e	regenerated with the HF update	2023-07-12 16:25:14 +02:00
d18c7db	c59bdec4f2	Unified fpga folders	2023-05-30 19:47:27 +02:00