mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-20 15:26:13 +08:00
30f2a7d38f
typo fixes in iso14443a code, added the missing "tools" directory, added initial elements for online/offline detection for commands.
233 lines
8.6 KiB
C
233 lines
8.6 KiB
C
//-----------------------------------------------------------------------------
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// Routines to load the FPGA image, and then to configure the FPGA's major
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// mode once it is configured.
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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#include <proxmark3.h>
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#include "apps.h"
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//-----------------------------------------------------------------------------
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// Set up the Serial Peripheral Interface as master
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// Used to write the FPGA config word
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// May also be used to write to other SPI attached devices like an LCD
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//-----------------------------------------------------------------------------
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void SetupSpi(int mode)
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{
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// PA10 -> SPI_NCS2 chip select (LCD)
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// PA11 -> SPI_NCS0 chip select (FPGA)
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// PA12 -> SPI_MISO Master-In Slave-Out
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// PA13 -> SPI_MOSI Master-Out Slave-In
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// PA14 -> SPI_SPCK Serial Clock
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// Disable PIO control of the following pins, allows use by the SPI peripheral
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PIO_DISABLE = (1 << GPIO_NCS0) |
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(1 << GPIO_NCS2) |
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(1 << GPIO_MISO) |
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(1 << GPIO_MOSI) |
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(1 << GPIO_SPCK);
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PIO_PERIPHERAL_A_SEL = (1 << GPIO_NCS0) |
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(1 << GPIO_MISO) |
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(1 << GPIO_MOSI) |
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(1 << GPIO_SPCK);
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PIO_PERIPHERAL_B_SEL = (1 << GPIO_NCS2);
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//enable the SPI Peripheral clock
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PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);
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// Enable SPI
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SPI_CONTROL = SPI_CONTROL_ENABLE;
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switch (mode) {
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case SPI_FPGA_MODE:
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SPI_MODE =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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SPI_FOR_CHIPSEL_0 =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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( 8 << 4) | // Bits per Transfer (16 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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case SPI_LCD_MODE:
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SPI_MODE =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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SPI_FOR_CHIPSEL_2 =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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( 1 << 4) | // Bits per Transfer (9 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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default: // Disable SPI
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SPI_CONTROL = SPI_CONTROL_DISABLE;
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break;
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}
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}
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//-----------------------------------------------------------------------------
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// Set up the synchronous serial port, with the one set of options that we
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// always use when we are talking to the FPGA. Both RX and TX are enabled.
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//-----------------------------------------------------------------------------
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void FpgaSetupSsc(void)
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{
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// First configure the GPIOs, and get ourselves a clock.
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PIO_PERIPHERAL_A_SEL = (1 << GPIO_SSC_FRAME) |
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(1 << GPIO_SSC_DIN) |
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(1 << GPIO_SSC_DOUT) |
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(1 << GPIO_SSC_CLK);
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PIO_DISABLE = (1 << GPIO_SSC_DOUT);
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PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);
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// Now set up the SSC proper, starting from a known state.
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SSC_CONTROL = SSC_CONTROL_RESET;
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// RX clock comes from TX clock, RX starts when TX starts, data changes
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// on RX clock rising edge, sampled on falling edge
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SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
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// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
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// pulse, no output sync, start on positive-going edge of sync
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SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |
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SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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// clock comes from TK pin, no clock output, outputs change on falling
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// edge of TK, start on rising edge of TF
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SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |
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SSC_CLOCK_MODE_START(5);
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// tx framing is the same as the rx framing
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SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;
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SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;
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}
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//-----------------------------------------------------------------------------
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// Set up DMA to receive samples from the FPGA. We will use the PDC, with
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// a single buffer as a circular buffer (so that we just chain back to
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// ourselves, not to another buffer). The stuff to manipulate those buffers
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// is in apps.h, because it should be inlined, for speed.
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//-----------------------------------------------------------------------------
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void FpgaSetupSscDma(BYTE *buf, int len)
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{
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PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;
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PDC_RX_COUNTER(SSC_BASE) = len;
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PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;
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PDC_RX_NEXT_COUNTER(SSC_BASE) = len;
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PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;
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}
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//-----------------------------------------------------------------------------
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// Download the FPGA image stored in flash (slave serial).
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//-----------------------------------------------------------------------------
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void FpgaDownloadAndGo(void)
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{
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// FPGA image lives in FLASH at base address 0x2000
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// The current board design can not accomodate anything bigger than a XC2S30
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// FPGA and the config file size is fixed at 336,768 bits = 10,524 DWORDs
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const DWORD *FpgaImage=((DWORD *)0x2000);
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const DWORD FpgaImageLen=10524;
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int i, j;
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PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);
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PIO_ENABLE = (1 << GPIO_FPGA_ON);
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PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);
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SpinDelay(50);
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LED_D_ON();
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HIGH(GPIO_FPGA_NPROGRAM);
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LOW(GPIO_FPGA_CCLK);
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LOW(GPIO_FPGA_DIN);
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PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) |
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(1 << GPIO_FPGA_CCLK) |
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(1 << GPIO_FPGA_DIN);
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SpinDelay(1);
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LOW(GPIO_FPGA_NPROGRAM);
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SpinDelay(50);
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HIGH(GPIO_FPGA_NPROGRAM);
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for(i = 0; i < FpgaImageLen; i++) {
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DWORD v = FpgaImage[i];
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for(j = 0; j < 32; j++) {
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if(v & 0x80000000) {
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HIGH(GPIO_FPGA_DIN);
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} else {
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LOW(GPIO_FPGA_DIN);
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}
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HIGH(GPIO_FPGA_CCLK);
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LOW(GPIO_FPGA_CCLK);
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v <<= 1;
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}
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}
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LED_D_OFF();
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}
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//-----------------------------------------------------------------------------
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// Send a 16 bit command/data pair to the FPGA.
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// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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// where C is the 4 bit command and D is the 12 bit data
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//-----------------------------------------------------------------------------
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void FpgaSendCommand(WORD cmd, WORD v)
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{
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SetupSpi(SPI_FPGA_MODE);
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while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete
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SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v; // send the data
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}
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//-----------------------------------------------------------------------------
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// Write the FPGA setup word (that determines what mode the logic is in, read
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// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
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// avoid changing this function's occurence everywhere in the source code.
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//-----------------------------------------------------------------------------
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void FpgaWriteConfWord(BYTE v)
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{
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FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
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}
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//-----------------------------------------------------------------------------
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// Set up the CMOS switches that mux the ADC: four switches, independently
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// closable, but should only close one at a time. Not an FPGA thing, but
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// the samples from the ADC always flow through the FPGA.
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//-----------------------------------------------------------------------------
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void SetAdcMuxFor(int whichGpio)
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{
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PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |
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(1 << GPIO_MUXSEL_LOPKD) |
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(1 << GPIO_MUXSEL_LORAW) |
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(1 << GPIO_MUXSEL_HIRAW);
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PIO_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |
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(1 << GPIO_MUXSEL_LOPKD) |
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(1 << GPIO_MUXSEL_LORAW) |
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(1 << GPIO_MUXSEL_HIRAW);
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LOW(GPIO_MUXSEL_HIPKD);
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LOW(GPIO_MUXSEL_HIRAW);
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LOW(GPIO_MUXSEL_LORAW);
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LOW(GPIO_MUXSEL_LOPKD);
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HIGH(whichGpio);
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}
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