| .. | 
		
		
			
			
			
			
				| tests | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| clk_divider.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| define.v | After testing and verification its found that the SHALLOW MODULATION in HF is not working well in RDV4.  Swapping from PWR_OE4 to PWR_OE1 makes it much better. Thanks to @d18c7db for solution and @gentlekiwi for testing and never giving up on finding the bug | 2023-08-28 12:00:44 +02:00 | 
		
			
			
			
			
				| fpga_icopyx_felica.bit | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| fpga_icopyx_hf.bit | new fpga images | 2023-08-29 16:46:52 +02:00 | 
		
			
			
			
			
				| fpga_icopyx_hf.v | Removed commented out includes | 2023-08-24 18:06:44 +02:00 | 
		
			
			
			
			
				| fpga_icopyx_hf_15.bit | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| fpga_icopyx_lf.bit | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| fpga_icopyx_lf.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| fpga_icopyx_top.v | Removed commented out includes | 2023-08-24 18:06:44 +02:00 | 
		
			
			
			
			
				| fpga_pm3_felica.bit | new fpga images | 2023-08-29 16:46:52 +02:00 | 
		
			
			
			
			
				| fpga_pm3_hf.bit | new fpga images | 2023-08-29 16:46:52 +02:00 | 
		
			
			
			
			
				| fpga_pm3_hf_15.bit | new fpga images | 2023-08-29 16:46:52 +02:00 | 
		
			
			
			
			
				| fpga_pm3_lf.bit | new fpga images | 2023-08-29 16:46:52 +02:00 | 
		
			
			
			
			
				| fpga_pm3_top.v | Removed commented out includes | 2023-08-24 18:06:44 +02:00 | 
		
			
			
			
			
				| hi_flite.v | style | 2023-09-07 20:13:18 +02:00 | 
		
			
			
			
			
				| hi_get_trace.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| hi_iso14443a.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| hi_reader.v | ensure registers and vars is set correct | 2023-08-28 15:34:36 +02:00 | 
		
			
			
			
			
				| hi_simulate.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| hi_sniffer.v | Redundant check | 2023-08-29 11:26:43 +02:00 | 
		
			
			
			
			
				| lf_edge_detect.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| lo_adc.v | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| lo_edge_detect.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| lo_passthru.v | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| lo_read.v | More compact notation | 2023-08-29 11:24:56 +02:00 | 
		
			
			
			
			
				| lo_simulate.v | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| lp20khz_1MSa_iir_filter.v | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| Makefile | Merged hi_reader and hi_reader_15 into one file | 2023-08-24 17:52:12 +02:00 | 
		
			
			
			
			
				| min_max_tracker.v | Whitespace, formatting | 2023-08-24 18:21:07 +02:00 | 
		
			
			
			
			
				| mux2_onein.v | Removed commented out includes | 2023-08-24 18:06:44 +02:00 | 
		
			
			
			
			
				| mux2_oneout.v | Removed commented out includes | 2023-08-24 18:06:44 +02:00 | 
		
			
			
			
			
				| mux8.v | Removed commented out includes | 2023-08-24 18:06:44 +02:00 | 
		
			
			
			
			
				| mux16.v | Removed commented out includes | 2023-08-24 18:06:44 +02:00 | 
		
			
			
			
			
				| xc2s30-5-vq100.ucf | Unified fpga folders | 2023-05-30 19:47:27 +02:00 | 
		
			
			
			
			
				| xc3s100e-4-vq100.ucf | Unified fpga folders | 2023-05-30 19:47:27 +02:00 |