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30 lines
926 B
Verilog
30 lines
926 B
Verilog
//-----------------------------------------------------------------------------
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// For reading TI tags, we need to place the FPGA in pass through mode
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// and pass everything through to the ARM
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//-----------------------------------------------------------------------------
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// iZsh <izsh at fail0verflow.com>, June 2014
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module lo_passthru(
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input pck_divclk,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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output adc_clk,
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output ssp_din, input ssp_dout,
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input cross_lo,
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output dbg
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);
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// the antenna is modulated when ssp_dout = 1, when 0 the
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// antenna drivers stop modulating and go into listen mode
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assign pwr_oe3 = 1'b0;
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assign pwr_oe1 = ssp_dout;
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assign pwr_oe2 = ssp_dout;
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assign pwr_oe4 = ssp_dout;
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assign pwr_lo = pck_divclk && ssp_dout;
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assign pwr_hi = 1'b0;
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assign adc_clk = 1'b0;
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assign ssp_din = cross_lo;
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assign dbg = cross_lo;
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endmodule
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