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194 lines
7.1 KiB
Verilog
194 lines
7.1 KiB
Verilog
//-----------------------------------------------------------------------------
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// The FPGA is responsible for interfacing between the A/D, the coil drivers,
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// and the ARM. In the low-frequency modes it passes the data straight
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// through, so that the ARM gets raw A/D samples over the SSP. In the high-
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// frequency modes, the FPGA might perform some demodulation first, to
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// reduce the amount of data that we must send to the ARM.
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//
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// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
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// could be improved.
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//
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// Jonathan Westhues, March 2006
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// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
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// iZsh <izsh at fail0verflow.com>, June 2014
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// Piwi, Feb 2019
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//-----------------------------------------------------------------------------
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//For ISE 10.1 PROJ,IDE cannot apply definition to all files
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`include "define.v"
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//For ISE 10.1 PROJ,IDE auto include
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//`include "hi_reader.v"
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//`include "hi_simulate.v"
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//`include "hi_iso14443a.v"
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//`include "hi_sniffer.v"
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//`include "util.v"
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//`include "hi_flite.v"
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//`include "hi_get_trace.v"
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module fpga_hfmod(
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input spck, output miso, input mosi, input ncs,
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input pck0, input ck_1356meg, input ck_1356megb,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk, output adc_noe,
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output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
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input cross_hi, input cross_lo,
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output dbg
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);
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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/*
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Attempt to write up how its hooked up. Iceman 2020.
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Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
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Send 16 bit command / data pair to FPGA
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The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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where
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C is 4bit command
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D is 12bit data
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shift_reg receive this 16bit frame
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-----+--------- frame layout --------------------
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bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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-----+-------------------------------------------
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cmd | x x x x
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major| x x x
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opt | x x x
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divi | x x x x x x x x
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thres| x x x x x x x x
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-----+-------------------------------------------
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*/
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reg [15:0] shift_reg;
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reg [8:0] conf_word;
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reg trace_enable;
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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// from it, which means that we must make sure that we can do so without
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// glitching, or else we will glitch the transmitted carrier.
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
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`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
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endcase
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end
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always @(posedge spck)
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begin
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if(~ncs)
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begin
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shift_reg[15:1] <= shift_reg[14:0];
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shift_reg[0] <= mosi;
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end
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end
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// select module (outputs) based on major mode
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wire [2:0] major_mode = conf_word[8:6];
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// configuring the HF reader
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wire [1:0] subcarrier_frequency = conf_word[5:4];
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wire [3:0] minor_mode = conf_word[3:0];
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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// 000 - HF reader
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hi_reader hr(
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ck_1356megb,
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hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
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adc_d, hr_adc_clk,
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hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
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hr_dbg,
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subcarrier_frequency, minor_mode
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);
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// 001 - HF simulated tag
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hi_simulate hs(
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ck_1356meg,
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hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
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adc_d, hs_adc_clk,
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hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
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hs_dbg,
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minor_mode
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);
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// 010 - HF ISO14443-A
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hi_iso14443a hisn(
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ck_1356meg,
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hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
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adc_d, hisn_adc_clk,
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hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
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hisn_dbg,
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minor_mode
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);
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// 011 - HF sniff
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hi_sniffer he(
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ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, he_ssp_clk
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);
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// 100 - HF ISO18092 FeliCa
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hi_flite hfl(
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ck_1356megb,
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hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
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adc_d, hfl_adc_clk,
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hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
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hfl_dbg,
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minor_mode
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);
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// 101 - HF get trace
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hi_get_trace gt(
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ck_1356megb,
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adc_d, trace_enable, major_mode,
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gt_ssp_frame, gt_ssp_din, gt_ssp_clk
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);
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// Major modes:
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// 000 -- HF reader; subcarrier frequency and modulation depth selectable
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// 001 -- HF simulated tag
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// 010 -- HF ISO14443-A
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// 011 -- HF sniff
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// 100 -- HF ISO18092 FeliCa
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// 101 -- HF get trace
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// 110 -- unused
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// 111 -- FPGA_MAJOR_MODE_OFF
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// 000 001 010 011 100 101 110 111
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mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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endmodule
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