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41 lines
1.2 KiB
Verilog
41 lines
1.2 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// General-purpose miscellany.
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//
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module mux8(sel, y, x0, x1, x2, x3, x4, x5, x6, x7);
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input [2:0] sel;
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input x0, x1, x2, x3, x4, x5, x6, x7;
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output y;
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reg y;
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always @(x0 or x1 or x2 or x3 or x4 or x5 or x6 or x7 or sel)
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begin
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case (sel)
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3'b000: y = x0;
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3'b001: y = x1;
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3'b010: y = x2;
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3'b011: y = x3;
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3'b100: y = x4;
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3'b101: y = x5;
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3'b110: y = x6;
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3'b111: y = x7;
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endcase
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end
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endmodule
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