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77 lines
2.7 KiB
Verilog
77 lines
2.7 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// input clk is 24MHz
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`include "min_max_tracker.v"
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module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,
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output [7:0] max, output [7:0] min,
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output [7:0] high_threshold, output [7:0] highz_threshold,
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output [7:0] lowz_threshold, output [7:0] low_threshold,
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output edge_state, output edge_toggle);
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min_max_tracker tracker(clk, adc_d, lf_ed_threshold, min, max);
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// auto-tune
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assign high_threshold = (max + min) / 2 + (max - min) / 4;
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assign highz_threshold = (max + min) / 2 + (max - min) / 8;
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assign lowz_threshold = (max + min) / 2 - (max - min) / 8;
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assign low_threshold = (max + min) / 2 - (max - min) / 4;
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// heuristic to see if it makes sense to try to detect an edge
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wire enabled =
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(high_threshold > highz_threshold)
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& (highz_threshold > lowz_threshold)
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& (lowz_threshold > low_threshold)
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& ((high_threshold - highz_threshold) > 8)
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& ((highz_threshold - lowz_threshold) > 16)
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& ((lowz_threshold - low_threshold) > 8);
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// Toggle the output with hysteresis
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// Set to high if the ADC value is above the threshold
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// Set to low if the ADC value is below the threshold
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reg is_high = 0;
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reg is_low = 0;
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reg is_zero = 0;
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reg trigger_enabled = 1;
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reg output_edge = 0;
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reg output_state;
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always @(posedge clk)
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begin
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is_high <= (adc_d >= high_threshold);
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is_low <= (adc_d <= low_threshold);
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is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold));
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end
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// all edges detection
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always @(posedge clk)
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if (enabled) begin
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// To enable detecting two consecutive peaks at the same level
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// (low or high) we check whether or not we went back near 0 in-between.
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// This extra check is necessary to prevent from noise artifacts
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// around the threshold values.
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if (trigger_enabled & (is_high | is_low)) begin
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output_edge <= ~output_edge;
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trigger_enabled <= 0;
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end else
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trigger_enabled <= trigger_enabled | is_zero;
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end
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// edge states
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always @(posedge clk)
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if (enabled) begin
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if (is_high)
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output_state <= 1'd1;
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else if (is_low)
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output_state <= 1'd0;
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end
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assign edge_state = output_state;
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assign edge_toggle = output_edge;
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endmodule
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