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https://github.com/RfidResearchGroup/proxmark3.git
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3b2fee43ea
This is a new LF edge detection algorithm for the FPGA. - It uses a low-pass IIR filter to clean the signal (see https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html) - The algorithm is able to detect consecutive peaks in the same direction - It uses an envelope follower to dynamically adjust the peak thresholds - The main threshold used in the envelope follower can be set from the ARM side fpga/lf_edge_detect.v, fpga/lp20khz_1MSa_iir_filter.v, fpga/min_max_tracker.v: New file. fpga/lo_edge_detect.v, fpga/fpga_lf.v: Modify accordingly. armsrc/apps.h (FPGA_CMD_SET_USER_BYTE1, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD): New FPGA command. fpga/fpga_lf.v: Modify accordingly/Add a 8bit user register. fpga/fpga_lf.bit: Update accordingly. fpga/tests: New directory for testbenches fpga/tests/Makefile: New file. It compiles the testbenches and runs all the tests by default (comparing with the golden output) fpga/tests/tb_lp20khz_1MSa_iir_filter.v, fpga/tests/tb_min_max_tracker.v, fpga/tests/tb_lf_edge_detect.v: New testbenches fpga/tests/plot_edgedetect.py: New script to plot the results from the edge detection tests. fpga/tests/tb_data: New directory for data and golden outputs
74 lines
1.5 KiB
Verilog
74 lines
1.5 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// testbench for min_max_tracker
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`include "min_max_tracker.v"
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`define FIN "tb_tmp/data.filtered.gold"
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`define FOUT_MIN "tb_tmp/data.min"
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`define FOUT_MAX "tb_tmp/data.max"
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module min_max_tracker_tb;
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integer fin;
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integer fout_min, fout_max;
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integer r;
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reg clk;
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reg [7:0] adc_d;
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wire [7:0] min;
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wire [7:0] max;
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initial
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begin
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clk = 0;
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fin = $fopen(`FIN, "r");
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if (!fin) begin
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$display("ERROR: can't open the data file");
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$finish;
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end
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fout_min = $fopen(`FOUT_MIN, "w+");
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fout_max = $fopen(`FOUT_MAX, "w+");
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if (!$feof(fin))
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adc_d = $fgetc(fin); // read the first value
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end
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always
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# 1 clk = !clk;
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// input
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initial
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begin
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while (!$feof(fin)) begin
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@(negedge clk) adc_d <= $fgetc(fin);
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end
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if ($feof(fin))
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begin
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# 3 $fclose(fin);
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$fclose(fout_min);
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$fclose(fout_max);
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$finish;
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end
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end
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initial
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begin
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// $monitor("%d\t min: %x, max: %x", $time, min, max);
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end
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// output
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always @(negedge clk)
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if ($time > 2) begin
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r = $fputc(min, fout_min);
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r = $fputc(max, fout_max);
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end
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// module to test
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min_max_tracker tracker(clk, adc_d, 8'd127, min, max);
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endmodule |