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105 lines
3 KiB
Verilog
105 lines
3 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The way that we connect things in low-frequency simulation mode. In this
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// case just pass everything through to the ARM, which can bit-bang this
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// (because it is so slow).
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module lo_adc(
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input pck0,
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input [7:0] adc_d,
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input [7:0] divisor,
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input lf_field,
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input ssp_dout,
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output ssp_din,
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output ssp_frame,
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output ssp_clk,
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output adc_clk,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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output debug
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);
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reg [7:0] to_arm_shiftreg;
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reg [7:0] pck_divider;
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reg clk_state;
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// Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
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wire tag_modulation = ssp_dout & !lf_field;
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wire reader_modulation = !ssp_dout & lf_field & clk_state;
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// always on (High Frequency outputs, unused)
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assign pwr_oe1 = 1'b0;
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assign pwr_hi = 1'b0;
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// low frequency outputs
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assign pwr_lo = reader_modulation;
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assign pwr_oe2 = 1'b0; // 33 Ohms
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assign pwr_oe3 = tag_modulation; // base antenna load = 33 Ohms
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assign pwr_oe4 = 1'b0; // 10k Ohms
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// Debug Output ADC clock
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assign debug = adc_clk;
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// ADC clock out of phase with antenna driver
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assign adc_clk = ~clk_state;
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// serialized SSP data is gated by clk_state to suppress unwanted signal
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assign ssp_din = to_arm_shiftreg[7] && !clk_state;
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// SSP clock always runs at 24MHz
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assign ssp_clk = pck0;
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// SSP frame is gated by clk_state and goes high when pck_divider=8..15
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assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;
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// divide 24mhz down to 3mhz
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always @(posedge pck0)
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begin
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if (pck_divider == divisor[7:0])
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begin
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pck_divider <= 8'd0;
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clk_state = !clk_state;
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end
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else
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begin
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pck_divider <= pck_divider + 1;
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end
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end
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// this task also runs at pck0 frequency (24Mhz) and is used to serialize
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// the ADC output which is then clocked into the ARM SSP.
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always @(posedge pck0)
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begin
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if ((pck_divider == 8'd7) && !clk_state)
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to_arm_shiftreg <= adc_d;
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else
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begin
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to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
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to_arm_shiftreg[0] <= 1'b0;
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end
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end
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endmodule
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