mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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3b2fee43ea
This is a new LF edge detection algorithm for the FPGA. - It uses a low-pass IIR filter to clean the signal (see https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html) - The algorithm is able to detect consecutive peaks in the same direction - It uses an envelope follower to dynamically adjust the peak thresholds - The main threshold used in the envelope follower can be set from the ARM side fpga/lf_edge_detect.v, fpga/lp20khz_1MSa_iir_filter.v, fpga/min_max_tracker.v: New file. fpga/lo_edge_detect.v, fpga/fpga_lf.v: Modify accordingly. armsrc/apps.h (FPGA_CMD_SET_USER_BYTE1, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD): New FPGA command. fpga/fpga_lf.v: Modify accordingly/Add a 8bit user register. fpga/fpga_lf.bit: Update accordingly. fpga/tests: New directory for testbenches fpga/tests/Makefile: New file. It compiles the testbenches and runs all the tests by default (comparing with the golden output) fpga/tests/tb_lp20khz_1MSa_iir_filter.v, fpga/tests/tb_min_max_tracker.v, fpga/tests/tb_lf_edge_detect.v: New testbenches fpga/tests/plot_edgedetect.py: New script to plot the results from the edge detection tests. fpga/tests/tb_data: New directory for data and golden outputs
39 lines
1.2 KiB
Makefile
39 lines
1.2 KiB
Makefile
include ../common/Makefile.common
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all: fpga_lf.bit fpga_hf.bit
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clean:
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$(DELETE) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp
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$(DELETE) *.map *.ngc *.xrpt *.pcf *.rbt *_auto_* *.bld *.mrp *.ngm *.unroutes *_summary.xml netlist.lst xst
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fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_read_tx.v hi_read_rx_xcorr.v hi_iso14443a.v
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf.scr
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fpga_lf.ngc: fpga_lf.v fpga.ucf xst_lf.scr util.v clk_divider.v lo_edge_detect.v lo_read.v lo_passthru.v lp20khz_1MSa_iir_filter.v min_max_tracker.v lf_edge_detect.v
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)xst -ifn xst_lf.scr
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%.ngd: %.ngc
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)ngdbuild -aul -p xc2s30-5-vq100 -nt timestamp -uc fpga.ucf $< $@
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%.ncd: %.ngd
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)map -p xc2s30-5-vq100 $<
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%-placed.ncd: %.ncd
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)par $< $@
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%.bit: %-placed.ncd
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$(DELETE) $@ $*.drc $*.rbt
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$(XILINX_TOOLS_PREFIX)bitgen $< $@
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.PHONY: all clean help
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help:
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@echo Multi-OS Makefile, you are running on $(DETECTED_OS)
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@echo Possible targets:
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@echo + all - Make fpga.bit, the FPGA bitstream
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@echo + clean - Clean intermediate files, does not clean fpga.bit
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