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125 lines
4.5 KiB
Verilog
125 lines
4.5 KiB
Verilog
//-----------------------------------------------------------------------------
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// Jonathan Westhues, March 2006
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// iZsh <izsh at fail0verflow.com>, June 2014
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//-----------------------------------------------------------------------------
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`include "lo_read.v"
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`include "lo_passthru.v"
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`include "lo_edge_detect.v"
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`include "util.v"
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`include "clk_divider.v"
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module fpga_lf(
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input spck, output miso, input mosi, input ncs,
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input pck0, input ck_1356meg, input ck_1356megb,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk, output adc_noe,
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output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
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input cross_hi, input cross_lo,
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output dbg
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);
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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reg [15:0] shift_reg;
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reg [7:0] divisor;
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reg [7:0] conf_word;
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reg [7:0] user_byte1;
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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4'b0001:
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begin
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conf_word <= shift_reg[7:0];
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if (shift_reg[7:0] == 8'b00000001) begin // LF edge detect
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user_byte1 <= 127; // default threshold
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end
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end
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4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
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4'b0011: user_byte1 <= shift_reg[7:0]; // FPGA_CMD_SET_USER_BYTE1
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endcase
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end
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always @(posedge spck)
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begin
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if(~ncs)
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begin
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shift_reg[15:1] <= shift_reg[14:0];
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shift_reg[0] <= mosi;
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end
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end
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wire [2:0] major_mode = conf_word[7:5];
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// For the low-frequency configuration:
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wire lf_field = conf_word[0];
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wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
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wire [7:0] lf_ed_threshold = user_byte1;
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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wire [7:0] pck_cnt;
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wire pck_divclk;
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clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
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lo_read lr(
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pck0, pck_cnt, pck_divclk,
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lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
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adc_d, lr_adc_clk,
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lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
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lr_dbg, lf_field
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);
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lo_passthru lp(
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pck_divclk,
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lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
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lp_adc_clk,
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lp_ssp_din, ssp_dout,
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cross_lo,
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lp_dbg
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);
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lo_edge_detect le(
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pck0, pck_divclk,
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le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
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adc_d, le_adc_clk,
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le_ssp_frame, ssp_dout, le_ssp_clk,
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cross_lo,
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le_dbg,
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lf_field,
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lf_ed_toggle_mode, lf_ed_threshold
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);
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// Major modes:
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// 000 -- LF reader (generic)
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// 001 -- LF edge detect (generic)
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// 010 -- LF passthrough
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// 110 -- FPGA_MAJOR_MODE_OFF_LF (rdv40 specific)
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// 111 -- FPGA_MAJOR_MODE_OFF
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// 000 001 010 011 100 101 110 111
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mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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endmodule
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