mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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82 lines
3.8 KiB
Verilog
82 lines
3.8 KiB
Verilog
//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 16:09:14 05/13/2020
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// Design Name:
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// Module Name: fpga_all_in_one
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module fpga_hf(
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input spck, output miso, input mosi, input ncs,
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input pck0, input ck_1356meg, input ck_1356megb,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk, output adc_noe,
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output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
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input cross_hi, input cross_lo,
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output dbg,
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output PWR_LO_EN,
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input FPGA_SWITCH
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);
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fpga_hfmod hfmod(
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hfspck, hfmiso, hfmosi, hfncs,
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hfpck0, hfck_1356meg, hfck_1356megb,
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hfpwr_lo, hfpwr_hi,
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hfpwr_oe1, hfpwr_oe2, hfpwr_oe3, hfpwr_oe4,
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adc_d, hfadc_clk, hfadc_noe,
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hfssp_frame, hfssp_din, hfssp_dout, hfssp_clk,
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hfcross_hi, hfcross_lo,
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hfdbg
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);
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fpga_lfmod lfmod(
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lfspck, lfmiso, lfmosi, lfncs,
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lfpck0, lfck_1356meg, lfck_1356megb,
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lfpwr_lo, lfpwr_hi,
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lfpwr_oe1, lfpwr_oe2, lfpwr_oe3, lfpwr_oe4,
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adc_d, lfadc_clk, lfadc_noe,
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lfssp_frame, lfssp_din, lfssp_dout, lfssp_clk,
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lfcross_hi, lfcross_lo,
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lfdbg,
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lfPWR_LO_EN
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);
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mux2_oneout mux_spck_all (FPGA_SWITCH, spck, hfspck, lfspck);
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mux2_one mux_miso_all (FPGA_SWITCH, miso, hfmiso, lfmiso);
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mux2_oneout mux_mosi_all (FPGA_SWITCH, mosi, hfmosi, lfmosi);
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mux2_oneout mux_ncs_all (FPGA_SWITCH, ncs, hfncs, lfncs);
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mux2_oneout mux_pck0_all (FPGA_SWITCH, pck0, hfpck0, lfpck0);
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mux2_oneout mux_ck_1356meg_all (FPGA_SWITCH, ck_1356meg, hfck_1356meg, lfck_1356meg);
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mux2_oneout mux_ck_1356megb_all (FPGA_SWITCH, ck_1356megb, hfck_1356megb, lfck_1356megb);
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mux2_one mux_pwr_lo_all (FPGA_SWITCH, pwr_lo, hfpwr_lo, lfpwr_lo);
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mux2_one mux_pwr_hi_all (FPGA_SWITCH, pwr_hi, hfpwr_hi, lfpwr_hi);
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mux2_one mux_pwr_oe1_all (FPGA_SWITCH, pwr_oe1, hfpwr_oe1, lfpwr_oe1);
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mux2_one mux_pwr_oe2_all (FPGA_SWITCH, pwr_oe2, hfpwr_oe2, lfpwr_oe2);
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mux2_one mux_pwr_oe3_all (FPGA_SWITCH, pwr_oe3, hfpwr_oe3, lfpwr_oe3);
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mux2_one mux_pwr_oe4_all (FPGA_SWITCH, pwr_oe4, hfpwr_oe4, lfpwr_oe4);
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mux2_one mux_adc_clk_all (FPGA_SWITCH, adc_clk, hfadc_clk, lfadc_clk);
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mux2_one mux_adc_noe_all (FPGA_SWITCH, adc_noe, adc_noe, lfadc_noe);
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mux2_one mux_ssp_frame_all (FPGA_SWITCH, ssp_frame, hfssp_frame, lfssp_frame);
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mux2_one mux_ssp_din_all (FPGA_SWITCH, ssp_din, hfssp_din, lfssp_din);
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mux2_oneout mux_ssp_dout_all (FPGA_SWITCH, ssp_dout, hfssp_dout, lfssp_dout);
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mux2_one mux_ssp_clk_all (FPGA_SWITCH, ssp_clk, hfssp_clk, lfssp_clk);
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mux2_oneout mux_cross_hi_all (FPGA_SWITCH, cross_hi, hfcross_hi, lfcross_hi);
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mux2_oneout mux_cross_lo_all (FPGA_SWITCH, cross_lo, hfcross_lo, lfcross_lo);
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mux2_one mux_dbg_all (FPGA_SWITCH, dbg, hfdbg, lfdbg);
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mux2_one mux_PWR_LO_EN_all (FPGA_SWITCH, PWR_LO_EN, 1'b0, lfPWR_LO_EN);
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endmodule
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