mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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230 lines
8 KiB
C
230 lines
8 KiB
C
//-----------------------------------------------------------------------------
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// Iceman, July 2018
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// edits by - Anticat, August 2018
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// The main USART code, for serial communications over FPC connector
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//-----------------------------------------------------------------------------
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#include "usart.h"
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#include "string.h"
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#include "../armsrc/ticks.h" // startcountus
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volatile AT91PS_USART pUS1 = AT91C_BASE_US1;
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volatile AT91PS_PIO pPIO = AT91C_BASE_PIOA;
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volatile AT91PS_PDC pPDC = AT91C_BASE_PDC_US1;
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/*
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void usart_close(void) {
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// Reset the USART mode
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pUS1->US_MR = 0;
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// Reset the baud rate divisor register
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pUS1->US_BRGR = 0;
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// Reset the Timeguard Register
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pUS1->US_TTGR = 0;
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// Disable all interrupts
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pUS1->US_IDR = 0xFFFFFFFF;
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// Abort the Peripheral Data Transfers
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pUS1->US_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
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// Disable receiver and transmitter and stop any activity immediately
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pUS1->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
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}
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*/
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static uint8_t us_inbuf1[USART_BUFFLEN];
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static uint8_t us_inbuf2[USART_BUFFLEN];
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uint8_t *usart_cur_inbuf = NULL;
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uint16_t usart_cur_inbuf_off = 0;
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static uint8_t us_rxfifo[USART_FIFOLEN];
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static size_t us_rxfifo_low = 0;
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static size_t us_rxfifo_high = 0;
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static void usart_fill_rxfifo(void) {
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uint16_t rxfifo_free = 0;
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if (pUS1->US_RNCR == 0) { // One buffer got filled, backup buffer being used
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if (us_rxfifo_low > us_rxfifo_high)
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rxfifo_free = us_rxfifo_low - us_rxfifo_high;
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else
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rxfifo_free = sizeof(us_rxfifo) - us_rxfifo_high + us_rxfifo_low;
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uint16_t available = USART_BUFFLEN - usart_cur_inbuf_off;
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if (available <= rxfifo_free) {
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for (uint16_t i = 0; i < available; i++) {
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us_rxfifo[us_rxfifo_high++] = usart_cur_inbuf[usart_cur_inbuf_off + i];
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if (us_rxfifo_high == sizeof(us_rxfifo))
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us_rxfifo_high = 0;
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}
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// Give next buffer
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pUS1->US_RNPR = (uint32_t)usart_cur_inbuf;
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pUS1->US_RNCR = USART_BUFFLEN;
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// Swap current buff
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if (usart_cur_inbuf == us_inbuf1)
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usart_cur_inbuf = us_inbuf2;
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else
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usart_cur_inbuf = us_inbuf1;
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usart_cur_inbuf_off = 0;
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} else {
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// Take only what we have room for
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available = rxfifo_free;
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for (uint16_t i = 0; i < available; i++) {
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us_rxfifo[us_rxfifo_high++] = usart_cur_inbuf[usart_cur_inbuf_off + i];
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if (us_rxfifo_high == sizeof(us_rxfifo))
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us_rxfifo_high = 0;
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}
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usart_cur_inbuf_off += available;
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return;
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}
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}
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if (pUS1->US_RCR < USART_BUFFLEN - usart_cur_inbuf_off) { // Current buffer partially filled
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if (us_rxfifo_low > us_rxfifo_high)
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rxfifo_free = us_rxfifo_low - us_rxfifo_high;
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else
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rxfifo_free = sizeof(us_rxfifo) - us_rxfifo_high + us_rxfifo_low;
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uint16_t available = USART_BUFFLEN - pUS1->US_RCR - usart_cur_inbuf_off;
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if (available > rxfifo_free)
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available = rxfifo_free;
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for (uint16_t i = 0; i < available; i++) {
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us_rxfifo[us_rxfifo_high++] = usart_cur_inbuf[usart_cur_inbuf_off + i];
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if (us_rxfifo_high == sizeof(us_rxfifo))
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us_rxfifo_high = 0;
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}
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usart_cur_inbuf_off += available;
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}
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}
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uint16_t usart_rxdata_available(void) {
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usart_fill_rxfifo();
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if (us_rxfifo_low <= us_rxfifo_high)
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return us_rxfifo_high - us_rxfifo_low;
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else
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return sizeof(us_rxfifo) - us_rxfifo_low + us_rxfifo_high;
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}
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extern bool reply_via_fpc;
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extern void Dbprintf(const char *fmt, ...);
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#define Dbprintf_usb(...) {\
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bool tmp = reply_via_fpc;\
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reply_via_fpc = false;\
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Dbprintf(__VA_ARGS__);\
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reply_via_fpc = tmp;}
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uint32_t usart_read_ng(uint8_t *data, size_t len) {
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if (len == 0) return 0;
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uint32_t packetSize, nbBytesRcv = 0;
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uint32_t try = 0;
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// uint32_t highest_observed_try = 0;
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// Empirical max try observed: 3000000 / USART_BAUD_RATE
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// Let's take 10x
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uint32_t tryconstant = 0;
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#ifdef USART_SLOW_LINK
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// Experienced up to 13200 tries on BT link even at 460800
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tryconstant = 50000;
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#endif
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uint32_t maxtry = 10 * (3000000 / USART_BAUD_RATE) + tryconstant;
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while (len) {
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uint32_t available = usart_rxdata_available();
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packetSize = MIN(available, len);
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if (available > 0) {
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// Dbprintf_usb("Dbg USART ask %d bytes, available %d bytes, packetsize %d bytes", len, available, packetSize);
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// highest_observed_try = MAX(highest_observed_try, try);
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try = 0;
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}
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len -= packetSize;
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while (packetSize--) {
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data[nbBytesRcv++] = us_rxfifo[us_rxfifo_low++];
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if (us_rxfifo_low == sizeof(us_rxfifo))
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us_rxfifo_low = 0;
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}
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if (try++ == maxtry) {
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// Dbprintf_usb("Dbg USART TIMEOUT");
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break;
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}
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}
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// highest_observed_try = MAX(highest_observed_try, try);
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// Dbprintf_usb("Dbg USART max observed try %i", highest_observed_try);
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return nbBytesRcv;
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}
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// transfer from device to client
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inline int usart_writebuffer_sync(uint8_t *data, size_t len) {
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// Wait for current PDC bank to be free
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// (and check next bank too, in case there will be a usart_writebuffer_async)
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while (pUS1->US_TNCR || pUS1->US_TCR) {};
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pUS1->US_TPR = (uint32_t)data;
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pUS1->US_TCR = len;
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// Wait until finishing all transfers to make sure "data" buffer can be discarded
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// (if we don't wait here, bulk send as e.g. "hw status" will fail)
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while (pUS1->US_TNCR || pUS1->US_TCR) {};
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return PM3_SUCCESS;
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}
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void usart_init(void) {
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// For a nice detailed sample, interrupt driven but still relevant.
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// See https://www.sparkfun.com/datasheets/DevTools/SAM7/at91sam7%20serial%20communications.pdf
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// disable & reset receiver / transmitter for configuration
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pUS1->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS);
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//enable the USART1 Peripheral clock
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US1);
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// disable PIO control of receive / transmit pins
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pPIO->PIO_PDR |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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// enable peripheral mode A on receive / transmit pins
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pPIO->PIO_ASR |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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pPIO->PIO_BSR = 0;
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// enable pull-up on receive / transmit pins (see 31.5.1 I/O Lines)
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pPIO->PIO_PPUER |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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// set mode
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pUS1->US_MR = AT91C_US_USMODE_NORMAL | // normal mode
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AT91C_US_CLKS_CLOCK | // MCK (48MHz)
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AT91C_US_OVER | // oversampling
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AT91C_US_CHRL_8_BITS | // 8 bits
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AT91C_US_PAR_NONE | // parity: none
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AT91C_US_NBSTOP_1_BIT | // 1 stop bit
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AT91C_US_CHMODE_NORMAL; // channel mode: normal
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// all interrupts disabled
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pUS1->US_IDR = 0xFFFF;
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pUS1->US_BRGR = 48054841 / (USART_BAUD_RATE << 3);
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// Write the Timeguard Register
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pUS1->US_TTGR = 0;
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pUS1->US_RTOR = 0;
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pUS1->US_FIDI = 0;
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pUS1->US_IF = 0;
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// Initialize DMA buffers
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pUS1->US_TPR = (uint32_t)0;
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pUS1->US_TCR = 0;
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pUS1->US_TNPR = (uint32_t)0;
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pUS1->US_TNCR = 0;
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pUS1->US_RPR = (uint32_t)us_inbuf1;
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pUS1->US_RCR = USART_BUFFLEN;
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usart_cur_inbuf = us_inbuf1;
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pUS1->US_RNPR = (uint32_t)us_inbuf2;
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pUS1->US_RNCR = USART_BUFFLEN;
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// re-enable receiver / transmitter
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pUS1->US_CR = (AT91C_US_RXEN | AT91C_US_TXEN);
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// ready to receive and transmit
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pUS1->US_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
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}
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