mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-20 15:26:13 +08:00
431 lines
13 KiB
C
431 lines
13 KiB
C
//-----------------------------------------------------------------------------
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// Jonathan Westhues, Sept 2005
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// Utility functions used in many places, not specific to any piece of code.
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//-----------------------------------------------------------------------------
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#include "proxmark3.h"
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#include "util.h"
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#include "string.h"
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#include "apps.h"
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#include "BigBuf.h"
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void print_result(char *name, uint8_t *buf, size_t len) {
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uint8_t *p = buf;
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if ( len % 16 == 0 ) {
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for(; p-buf < len; p += 16)
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Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
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name,
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p-buf,
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len,
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p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
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);
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}
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else {
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for(; p-buf < len; p += 8)
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Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
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}
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}
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size_t nbytes(size_t nbits) {
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return (nbits >> 3)+((nbits % 8) > 0);
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}
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uint32_t SwapBits(uint32_t value, int nrbits) {
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uint32_t newvalue = 0;
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for(int i = 0; i < nrbits; i++) {
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newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
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}
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return newvalue;
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}
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void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
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{
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while (len--) {
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dest[len] = (uint8_t) n;
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n >>= 8;
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}
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}
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uint64_t bytes_to_num(uint8_t* src, size_t len)
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{
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uint64_t num = 0;
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while (len--)
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{
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num = (num << 8) | (*src);
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src++;
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}
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return num;
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}
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// RotateLeft - Ultralight, Desfire
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void rol(uint8_t *data, const size_t len){
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uint8_t first = data[0];
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for (size_t i = 0; i < len-1; i++) {
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data[i] = data[i+1];
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}
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data[len-1] = first;
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}
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void lsl (uint8_t *data, size_t len) {
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for (size_t n = 0; n < len - 1; n++) {
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data[n] = (data[n] << 1) | (data[n+1] >> 7);
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}
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data[len - 1] <<= 1;
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}
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int32_t le24toh (uint8_t data[3])
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{
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return (data[2] << 16) | (data[1] << 8) | data[0];
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}
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void LEDsoff()
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{
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LED_A_OFF();
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LED_B_OFF();
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LED_C_OFF();
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LED_D_OFF();
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}
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// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
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void LED(int led, int ms)
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{
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if (led & LED_RED)
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LED_C_ON();
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if (led & LED_ORANGE)
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LED_A_ON();
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if (led & LED_GREEN)
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LED_B_ON();
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if (led & LED_RED2)
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LED_D_ON();
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if (!ms)
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return;
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SpinDelay(ms);
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if (led & LED_RED)
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LED_C_OFF();
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if (led & LED_ORANGE)
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LED_A_OFF();
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if (led & LED_GREEN)
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LED_B_OFF();
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if (led & LED_RED2)
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LED_D_OFF();
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}
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// Determine if a button is double clicked, single clicked,
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// not clicked, or held down (for ms || 1sec)
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// In general, don't use this function unless you expect a
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// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
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int BUTTON_CLICKED(int ms)
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{
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// Up to 500ms in between clicks to mean a double click
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int ticks = (48000 * (ms ? ms : 1000)) >> 10;
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// If we're not even pressed, forget about it!
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if (!BUTTON_PRESS())
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return BUTTON_NO_CLICK;
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// Borrow a PWM unit for my real-time clock
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AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
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// 48 MHz / 1024 gives 46.875 kHz
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AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
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AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
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AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
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uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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int letoff = 0;
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for(;;)
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{
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uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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// We haven't let off the button yet
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if (!letoff)
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{
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// We just let it off!
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if (!BUTTON_PRESS())
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{
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letoff = 1;
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// reset our timer for 500ms
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start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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ticks = (48000 * (500)) >> 10;
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}
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// Still haven't let it off
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else
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// Have we held down a full second?
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if (now == (uint16_t)(start + ticks))
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return BUTTON_HOLD;
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}
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// We already let off, did we click again?
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else
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// Sweet, double click!
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if (BUTTON_PRESS())
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return BUTTON_DOUBLE_CLICK;
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// Have we ran out of time to double click?
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else
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if (now == (uint16_t)(start + ticks))
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// At least we did a single click
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return BUTTON_SINGLE_CLICK;
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WDT_HIT();
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}
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// We should never get here
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return BUTTON_ERROR;
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}
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// Determine if a button is held down
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int BUTTON_HELD(int ms)
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{
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// If button is held for one second
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int ticks = (48000 * (ms ? ms : 1000)) >> 10;
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// If we're not even pressed, forget about it!
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if (!BUTTON_PRESS())
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return BUTTON_NO_CLICK;
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// Borrow a PWM unit for my real-time clock
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AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
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// 48 MHz / 1024 gives 46.875 kHz
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AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
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AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
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AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
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uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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for(;;)
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{
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uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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// As soon as our button let go, we didn't hold long enough
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if (!BUTTON_PRESS())
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return BUTTON_SINGLE_CLICK;
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// Have we waited the full second?
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else
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if (now == (uint16_t)(start + ticks))
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return BUTTON_HOLD;
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WDT_HIT();
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}
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// We should never get here
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return BUTTON_ERROR;
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}
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// attempt at high resolution microsecond timer
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// beware: timer counts in 21.3uS increments (1024/48Mhz)
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void SpinDelayUs(int us)
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{
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int ticks = (48*us) >> 10;
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// Borrow a PWM unit for my real-time clock
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AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
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// 48 MHz / 1024 gives 46.875 kHz
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AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
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AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
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AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
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uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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for(;;) {
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uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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if (now == (uint16_t)(start + ticks))
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return;
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WDT_HIT();
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}
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}
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void SpinDelay(int ms)
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{
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// convert to uS and call microsecond delay function
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SpinDelayUs(ms*1000);
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}
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/* Similar to FpgaGatherVersion this formats stored version information
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* into a string representation. It takes a pointer to the struct version_information,
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* verifies the magic properties, then stores a formatted string, prefixed by
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* prefix in dst.
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*/
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void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
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{
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struct version_information *v = (struct version_information*)version_information;
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dst[0] = 0;
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strncat(dst, prefix, len-1);
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if(v->magic != VERSION_INFORMATION_MAGIC) {
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strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);
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return;
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}
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if(v->versionversion != 1) {
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strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);
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return;
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}
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if(!v->present) {
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strncat(dst, "Version information not available\n", len - strlen(dst) - 1);
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return;
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}
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strncat(dst, v->gitversion, len - strlen(dst) - 1);
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if(v->clean == 0) {
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strncat(dst, "-unclean", len - strlen(dst) - 1);
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} else if(v->clean == 2) {
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strncat(dst, "-suspect", len - strlen(dst) - 1);
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}
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strncat(dst, " ", len - strlen(dst) - 1);
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strncat(dst, v->buildtime, len - strlen(dst) - 1);
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strncat(dst, "\n", len - strlen(dst) - 1);
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}
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// -------------------------------------------------------------------------
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// timer lib
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// -------------------------------------------------------------------------
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// test procedure:
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//
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// ti = GetTickCount();
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// SpinDelay(1000);
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// ti = GetTickCount() - ti;
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// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
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void StartTickCount()
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{
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// This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
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// We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
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uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
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// set RealTimeCounter divider to count at 1kHz:
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AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
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// note: worst case precision is approx 2.5%
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}
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/*
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* Get the current count.
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*/
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uint32_t RAMFUNC GetTickCount(){
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return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
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}
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// -------------------------------------------------------------------------
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// microseconds timer
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// -------------------------------------------------------------------------
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void StartCountUS()
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{
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AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
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// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
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// fast clock
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
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AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
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AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
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AT91C_BASE_TC0->TC_RA = 1;
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AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
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AT91C_BASE_TCB->TCB_BCR = 1;
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}
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uint32_t RAMFUNC GetCountUS(){
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//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
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// By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
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return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
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}
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static uint32_t GlobalUsCounter = 0;
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uint32_t RAMFUNC GetDeltaCountUS(){
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uint32_t g_cnt = GetCountUS();
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uint32_t g_res = g_cnt - GlobalUsCounter;
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GlobalUsCounter = g_cnt;
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return g_res;
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}
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// -------------------------------------------------------------------------
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// Timer for iso14443 commands. Uses ssp_clk from FPGA
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// -------------------------------------------------------------------------
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void StartCountSspClk()
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{
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
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| AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
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| AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
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// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
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AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
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| AT91C_TC_CPCSTOP // Stop clock on RC compare
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| AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
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| AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
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| AT91C_TC_ENETRG // Enable external trigger event
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| AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
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| AT91C_TC_WAVE // Waveform Mode
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| AT91C_TC_AEEVT_SET // Set TIOA1 on external event
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| AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
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AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
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// use TC0 to count TIOA1 pulses
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
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| AT91C_TC_WAVE // Waveform Mode
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| AT91C_TC_WAVESEL_UP // just count
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| AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
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| AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
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AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
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AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
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// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
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AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
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AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
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| AT91C_TC_WAVE // Waveform Mode
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| AT91C_TC_WAVESEL_UP; // just count
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
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AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
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//
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// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present
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//
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while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
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while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
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while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
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// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
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// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
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AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
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// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
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// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
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// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
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// (just started with the transfer of the 4th Bit).
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// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
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// we can use the counter.
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while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
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}
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uint32_t RAMFUNC GetCountSspClk(){
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uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
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if ((tmp_count & 0x0000ffff) == 0) //small chance that we may have missed an increment in TC2
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return (AT91C_BASE_TC2->TC_CV << 16);
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return tmp_count;
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}
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