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https://github.com/RfidResearchGroup/proxmark3.git
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56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
//-----------------------------------------------------------------------------
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// For reading TI tags, we need to place the FPGA in pass through mode
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// and pass everything through to the ARM
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//-----------------------------------------------------------------------------
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module lo_passthru(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg, divisor
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input [7:0] divisor;
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reg [7:0] pck_divider;
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reg ant_lo;
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// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
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// which is high for (divisor+1) pck0 cycles and low for the same duration
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// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
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// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
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always @(posedge pck0)
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begin
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if(pck_divider == divisor[7:0])
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begin
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pck_divider <= 8'd0;
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ant_lo = !ant_lo;
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end
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else
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begin
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pck_divider <= pck_divider + 1;
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end
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end
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// the antenna is modulated when ssp_dout = 1, when 0 the
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// antenna drivers stop modulating and go into listen mode
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assign pwr_oe3 = 1'b0;
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assign pwr_oe1 = ssp_dout;
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assign pwr_oe2 = ssp_dout;
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assign pwr_oe4 = ssp_dout;
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assign pwr_lo = ant_lo && ssp_dout;
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assign pwr_hi = 1'b0;
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assign adc_clk = 1'b0;
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assign ssp_din = cross_lo;
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assign dbg = cross_lo;
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endmodule
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