mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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229 lines
9.7 KiB
C
229 lines
9.7 KiB
C
//-----------------------------------------------------------------------------
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// Jonathan Westhues, Sept 2005
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// Iceman, Sept 2016
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// Timers, Clocks functions used in LF or Legic where you would need detailed time.
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//-----------------------------------------------------------------------------
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#include "ticks.h"
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// attempt at high resolution microsecond timer
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// beware: timer counts in 21.3uS increments (1024/48Mhz)
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void SpinDelayUs(int us) {
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int ticks = (48 * us) >> 10;
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// Borrow a PWM unit for my real-time clock
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AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
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// 48 MHz / 1024 gives 46.875 kHz
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AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
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AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
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AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
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uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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for(;;) {
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uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
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if (now == (uint16_t)(start + ticks))
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return;
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WDT_HIT();
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}
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}
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void SpinDelay(int ms) {
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// convert to uS and call microsecond delay function
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SpinDelayUs(ms*1000);
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}
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// -------------------------------------------------------------------------
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// timer lib
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// -------------------------------------------------------------------------
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// test procedure:
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//
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// ti = GetTickCount();
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// SpinDelay(1000);
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// ti = GetTickCount() - ti;
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// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
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void StartTickCount(void) {
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// This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
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// We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
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uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
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// set RealTimeCounter divider to count at 1kHz:
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AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
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// note: worst case precision is approx 2.5%
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}
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/*
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* Get the current count.
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*/
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uint32_t RAMFUNC GetTickCount(void){
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return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
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}
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// -------------------------------------------------------------------------
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// microseconds timer
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// -------------------------------------------------------------------------
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void StartCountUS(void) {
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AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14);
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
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// fast clock
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// tick=1.5mks
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
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AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
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AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
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AT91C_BASE_TC0->TC_RA = 1;
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AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TCB->TCB_BCR = 1;
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while (AT91C_BASE_TC1->TC_CV >= 1);
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}
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uint32_t RAMFUNC GetCountUS(void){
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//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
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// By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
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return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
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}
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// -------------------------------------------------------------------------
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// Timer for iso14443 commands. Uses ssp_clk from FPGA
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// -------------------------------------------------------------------------
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void StartCountSspClk(void) {
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
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| AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
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| AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
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// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
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AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
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| AT91C_TC_CPCSTOP // Stop clock on RC compare
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| AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
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| AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
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| AT91C_TC_ENETRG // Enable external trigger event
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| AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
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| AT91C_TC_WAVE // Waveform Mode
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| AT91C_TC_AEEVT_SET // Set TIOA1 on external event
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| AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
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AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
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// use TC0 to count TIOA1 pulses
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
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| AT91C_TC_WAVE // Waveform Mode
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| AT91C_TC_WAVESEL_UP // just count
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| AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
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| AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
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AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
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AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
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// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
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AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
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AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
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| AT91C_TC_WAVE // Waveform Mode
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| AT91C_TC_WAVESEL_UP; // just count
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC0
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC1
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AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC2
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// synchronize the counter with the ssp_frame signal.
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// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present
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while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
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while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
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while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
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// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
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// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
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AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
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// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
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// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
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// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
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// (just started with the transfer of the 4th Bit).
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// The high word of the counter (TC2) will not reset until the low word (TC0) overflows.
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// Therefore need to wait quite some time before we can use the counter.
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while (AT91C_BASE_TC2->TC_CV >= 1);
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}
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void ResetSspClk(void) {
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//enable clock of timer and software trigger
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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while (AT91C_BASE_TC2->TC_CV >= 1);
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}
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uint32_t RAMFUNC GetCountSspClk(void) {
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uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
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if ((tmp_count & 0x0000ffff) == 0) //small chance that we may have missed an increment in TC2
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return (AT91C_BASE_TC2->TC_CV << 16);
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return tmp_count;
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}
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// -------------------------------------------------------------------------
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// Timer for bitbanging, or LF stuff when you need a very precis timer
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// 1us = 1.5ticks
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// -------------------------------------------------------------------------
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void StartTicks(void){
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//initialization of the timer
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// tc1 is higher 0xFFFF0000
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// tc0 is lower 0x0000FFFF
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AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14);
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
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AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
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AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
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AT91C_BASE_TC0->TC_RA = 1;
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AT91C_BASE_TC0->TC_RC = 0;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from TC0
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TCB->TCB_BCR = 1;
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// wait until timer becomes zero.
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while (AT91C_BASE_TC1->TC_CV >= 1);
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}
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// Wait - Spindelay in ticks.
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// if called with a high number, this will trigger the WDT...
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void WaitTicks(uint32_t ticks){
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if ( ticks == 0 ) return;
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ticks += GET_TICKS;
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while (GET_TICKS < ticks);
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}
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// Wait / Spindelay in us (microseconds)
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// 1us = 1.5ticks.
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void WaitUS(uint16_t us){
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if ( us == 0 ) return;
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WaitTicks( (uint32_t)(us * 1.5) );
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}
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void WaitMS(uint16_t ms){
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if (ms == 0) return;
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WaitTicks( (uint32_t)(ms * 1500) );
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}
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// Starts Clock and waits until its reset
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void ResetTicks(){
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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while (AT91C_BASE_TC1->TC_CV >= 1);
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}
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void ResetTimer(AT91PS_TC timer){
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timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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while(timer->TC_CV >= 1) ;
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}
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