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66b1758278
Include statements in individual files are not required when compiling the code the correct way as a project with an explicitly defined work library. The Makefile exactly replicates the compilation process of the ISE environment and generates the required project files.
33 lines
1,020 B
Verilog
33 lines
1,020 B
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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// 1 input to 2 outputs multiplexer
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module mux2_oneout(
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input [1:0] sel,
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input y,
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output reg x0,
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output reg x1
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);
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always @(*)
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begin
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case (sel)
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1'b0: x1 = y;
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1'b1: x0 = y;
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endcase
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end
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endmodule
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