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132 lines
5.4 KiB
Verilog
132 lines
5.4 KiB
Verilog
//-----------------------------------------------------------------------------
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// The FPGA is responsible for interfacing between the A/D, the coil drivers,
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// and the ARM. In the low-frequency modes it passes the data straight
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// through, so that the ARM gets raw A/D samples over the SSP. In the high-
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// frequency modes, the FPGA might perform some demodulation first, to
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// reduce the amount of data that we must send to the ARM.
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//
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// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
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// could be improved.
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//
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// Jonathan Westhues, March 2006
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// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
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// iZsh <izsh at fail0verflow.com>, June 2014
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// Satsuoni <>, October 2017 , added FeliCa support.
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//-----------------------------------------------------------------------------
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`include "hi_flite.v"
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`include "util.v"
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`include "hi_sniffer.v"
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module fpga_nfc(
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input spck, output miso, input mosi, input ncs,
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input pck0, input ck_1356meg, input ck_1356megb,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk, output adc_noe,
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output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
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input cross_hi, input cross_lo,
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output dbg
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);
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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reg [15:0] shift_reg;
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reg [7:0] conf_word;
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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// from it, which means that we must make sure that we can do so without
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// glitching, or else we will glitch the transmitted carrier.
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
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endcase
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end
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always @(posedge spck)
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begin
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if(~ncs)
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begin
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shift_reg[15:1] <= shift_reg[14:0];
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shift_reg[0] <= mosi;
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end
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end
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wire [2:0] major_mode;
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assign major_mode = conf_word[7:5];
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// For the high-frequency transmit configuration: modulation depth, either
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// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
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// some fraction of the buffers)
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//wire hi_read_tx_shallow_modulation = conf_word[0];
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// For the high-frequency receive correlator: frequency against which to
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// correlate.
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wire hi_read_rx_xcorr_848 = conf_word[0];
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// and whether to drive the coil (reader) or just short it (snooper)
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wire hi_read_rx_xcorr_snoop = conf_word[1];
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// divide subcarrier frequency by 4
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wire hi_read_rx_xcorr_quarter = conf_word[2];
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// For the high-frequency simulated tag: what kind of modulation to use.
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wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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hi_sniffer he(
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pck0, ck_1356meg, ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
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cross_hi, cross_lo,
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he_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
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);
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hi_flite hfl(
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pck0, ck_1356meg, ck_1356megb,
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hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
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adc_d, hfl_adc_clk,
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hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
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cross_hi, cross_lo,
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hfl_dbg,
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hi_simulate_mod_type
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);
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// Major modes:
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// no major modes here for now, except NFC demod/sim. Maybe I should remove mux at some point, unless I can think of more modes
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// 000 --
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// 001 --
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// 010 --
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// 011 --
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// 100 --
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// 101 -- HF NFC demod, just to copy it for now
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// 111 -- everything off
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mux8 mux_ssp_clk (major_mode, ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, he_ssp_clk, hfl_ssp_clk, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, he_ssp_din, hfl_ssp_din, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, he_ssp_frame, hfl_ssp_frame, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, 1'b0, 1'b0, 1'b0, 1'b0, hfl_dbg, hfl_dbg, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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endmodule
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