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103 lines
2.5 KiB
Verilog
103 lines
2.5 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The way that we connect things in low-frequency simulation mode. In this
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// case just pass everything through to the ARM, which can bit-bang this
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// (because it is so slow).
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module lo_simulate(
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input pck0,
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input ck_1356meg,
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input ck_1356megb,
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input [7:0] adc_d,
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input [7:0] divisor,
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input cross_hi,
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input cross_lo,
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input ssp_dout,
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output ssp_din,
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output ssp_frame,
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output ssp_clk,
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output adc_clk,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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output debug
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);
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// No logic, straight through.
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assign pwr_oe3 = 1'b0;
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assign pwr_oe1 = ssp_dout;
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assign pwr_oe2 = ssp_dout;
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assign pwr_oe4 = ssp_dout;
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assign ssp_clk = cross_lo;
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assign pwr_lo = 1'b0;
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assign pwr_hi = 1'b0;
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assign debug = ssp_frame;
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// Divide the clock to be used for the ADC
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reg [7:0] pck_divider;
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reg clk_state;
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always @(posedge pck0)
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begin
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if(pck_divider == divisor[7:0])
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begin
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pck_divider <= 8'd0;
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clk_state = !clk_state;
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end
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else
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begin
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pck_divider <= pck_divider + 1;
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end
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end
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assign adc_clk = ~clk_state;
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// Toggle the output with hysteresis
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// Set to high if the ADC value is above 200
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// Set to low if the ADC value is below 64
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reg is_high;
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reg is_low;
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reg output_state;
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always @(posedge pck0)
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begin
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if((pck_divider == 8'd7) && !clk_state) begin
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is_high = (adc_d >= 8'd191);
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is_low = (adc_d <= 8'd64);
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end
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end
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always @(posedge is_high or posedge is_low)
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begin
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if(is_high)
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output_state <= 1'd1;
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else if(is_low)
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output_state <= 1'd0;
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end
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assign ssp_frame = output_state;
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endmodule
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