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23 lines
397 B
Verilog
23 lines
397 B
Verilog
//-----------------------------------------------------------------------------
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// Two way MUX.
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//
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// kombi, 2020.05
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//-----------------------------------------------------------------------------
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module mux2_oneout(
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input [1:0] sel,
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input y,
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output reg x0,
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output reg x1
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);
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always @(*)
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begin
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case (sel)
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1'b0: x1 = y;
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1'b1: x0 = y;
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endcase
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end
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endmodule
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