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197 lines
6.5 KiB
Verilog
197 lines
6.5 KiB
Verilog
//-----------------------------------------------------------------------------
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module hi_read_rx_xcorr(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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xcorr_is_848, snoop, xcorr_quarter_freq
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input xcorr_is_848, snoop, xcorr_quarter_freq;
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// Carrier is steady on through this, unless we're snooping.
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assign pwr_hi = ck_1356megb & (~snoop);
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assign pwr_oe1 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = 1'b0;
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reg [2:0] fc_div;
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always @(negedge ck_1356megb)
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fc_div <= fc_div + 1;
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(* clock_signal = "yes" *) reg adc_clk; // sample frequency, always 16 * fc
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always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
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if (xcorr_is_848 & ~xcorr_quarter_freq) // fc = 847.5 kHz, standard ISO14443B
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adc_clk <= ck_1356megb;
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else if (~xcorr_is_848 & ~xcorr_quarter_freq) // fc = 423.75 kHz
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adc_clk <= fc_div[0];
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else if (xcorr_is_848 & xcorr_quarter_freq) // fc = 211.875 kHz
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adc_clk <= fc_div[1];
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else // fc = 105.9375 kHz
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adc_clk <= fc_div[2];
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// When we're a reader, we just need to do the BPSK demod; but when we're an
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// eavesdropper, we also need to pick out the commands sent by the reader,
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// using AM. Do this the same way that we do it for the simulated tag.
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reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
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reg [11:0] has_been_low_for;
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always @(negedge adc_clk)
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begin
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if(& adc_d[7:0]) after_hysteresis <= 1'b1;
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else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
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if(after_hysteresis)
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begin
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has_been_low_for <= 7'b0;
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end
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else
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begin
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if(has_been_low_for == 12'd4095)
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begin
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has_been_low_for <= 12'd0;
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after_hysteresis <= 1'b1;
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end
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else
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has_been_low_for <= has_been_low_for + 1;
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end
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end
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// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
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// so we need a 6-bit counter.
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reg [5:0] corr_i_cnt;
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// And a couple of registers in which to accumulate the correlations. Since
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// load modulation saturates the ADC we have to use a large enough register
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// 32 * 255 = 8160, which can be held in 13 bits. Add 1 bit for sign.
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//
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// The initial code assumed a phase shift of up to 25% and the accumulators were
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// 11 bits (32 * 255 * 0,25 = 2040), we will pack all bits exceeding 11 bits into
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// MSB. This prevents under/-overflows but preserves sensitivity on the lower end.
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reg signed [13:0] corr_i_accum;
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reg signed [13:0] corr_q_accum;
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// we will report maximum 8 significant bits
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reg signed [7:0] corr_i_out;
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reg signed [7:0] corr_q_out;
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// clock and frame signal for communication to ARM
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reg ssp_clk;
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reg ssp_frame;
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always @(negedge adc_clk)
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begin
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corr_i_cnt <= corr_i_cnt + 1;
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end
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// ADC data appears on the rising edge, so sample it on the falling edge
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always @(negedge adc_clk)
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begin
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// These are the correlators: we correlate against in-phase and quadrature
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// versions of our reference signal, and keep the (signed) result to
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// send out later over the SSP.
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if(corr_i_cnt == 6'd0)
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begin
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// send 10 bits of tag signal, 4 MSBs are stuffed into 2 MSB
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if(~corr_i_accum[13])
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corr_i_out <= {corr_i_accum[13],
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corr_i_accum[12] | corr_i_accum[11] | corr_i_accum[10],
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corr_i_accum[12] | corr_i_accum[11] | corr_i_accum[9],
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corr_i_accum[8:4]};
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else
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corr_i_out <= {corr_i_accum[13],
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corr_i_accum[12] & corr_i_accum[11] & corr_i_accum[10],
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corr_i_accum[12] & corr_i_accum[11] & corr_i_accum[9],
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corr_i_accum[8:4]};
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if(~corr_q_accum[13])
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corr_q_out <= {corr_q_accum[13],
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corr_q_accum[12] | corr_q_accum[11] | corr_q_accum[10],
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corr_q_accum[12] | corr_q_accum[11] | corr_q_accum[9],
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corr_q_accum[8:4]};
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else
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corr_q_out <= {corr_q_accum[13],
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corr_q_accum[12] & corr_q_accum[11] & corr_q_accum[10],
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corr_q_accum[12] & corr_q_accum[11] & corr_q_accum[9],
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corr_q_accum[8:4]};
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if(snoop)
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begin
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// replace LSB with 1 bit reader signal
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corr_i_out[0] <= after_hysteresis_prev_prev;
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corr_q_out[0] <= after_hysteresis_prev;
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after_hysteresis_prev_prev <= after_hysteresis;
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end
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corr_i_accum <= adc_d;
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corr_q_accum <= adc_d;
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end
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else
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begin
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if(corr_i_cnt[3])
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corr_i_accum <= corr_i_accum - adc_d;
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else
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corr_i_accum <= corr_i_accum + adc_d;
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if(corr_i_cnt[3] == corr_i_cnt[2]) // phase shifted by pi/2
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corr_q_accum <= corr_q_accum + adc_d;
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else
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corr_q_accum <= corr_q_accum - adc_d;
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end
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// The logic in hi_simulate.v reports 4 samples per bit. We report two
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// (I, Q) pairs per bit, so we should do 2 samples per pair.
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if(corr_i_cnt == 6'd32)
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after_hysteresis_prev <= after_hysteresis;
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// Then the result from last time is serialized and send out to the ARM.
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// We get one report each cycle, and each report is 16 bits, so the
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// ssp_clk should be the adc_clk divided by 64/16 = 4.
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if(corr_i_cnt[1:0] == 2'b10)
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ssp_clk <= 1'b0;
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if(corr_i_cnt[1:0] == 2'b00)
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begin
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ssp_clk <= 1'b1;
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// Don't shift if we just loaded new data, obviously.
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if(corr_i_cnt != 6'd0)
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begin
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corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
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corr_q_out[7:1] <= corr_q_out[6:0];
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end
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end
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// set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
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// (send two frames with 8 Bits each)
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if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
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ssp_frame = 1'b1;
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else
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ssp_frame = 1'b0;
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end
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assign ssp_din = corr_i_out[7];
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assign dbg = corr_i_cnt[3];
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// Unused.
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assign pwr_lo = 1'b0;
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assign pwr_oe2 = 1'b0;
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endmodule
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