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82 lines
2.3 KiB
Verilog
82 lines
2.3 KiB
Verilog
//-----------------------------------------------------------------------------
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// The way that we connect things in low-frequency simulation mode. In this
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// case just pass everything through to the ARM, which can bit-bang this
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// (because it is so slow).
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module lo_adc(
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pck0,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg, divisor,
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lo_is_125khz, lf_field
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);
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input pck0;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input [7:0] divisor;
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input lo_is_125khz; // redundant signal, no longer used anywhere
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input lf_field;
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reg [7:0] to_arm_shiftreg;
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reg [7:0] pck_divider;
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reg clk_state;
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// Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
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wire tag_modulation;
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assign tag_modulation = ssp_dout & !lf_field;
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wire reader_modulation;
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assign reader_modulation = !ssp_dout & lf_field & clk_state;
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assign pwr_oe1 = 1'b0; // not used in LF mode
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assign pwr_oe2 = 1'b0; //tag_modulation;
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assign pwr_oe3 = tag_modulation;
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assign pwr_oe4 = 1'b0; //tag_modulation;
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assign pwr_lo = reader_modulation;
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assign pwr_hi = 1'b0;
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assign dbg = adc_clk;
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// ADC clock out of phase with antenna driver
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assign adc_clk = ~clk_state;
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// serialized SSP data is gated by clk_state to suppress unwanted signal
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assign ssp_din = to_arm_shiftreg[7] && !clk_state;
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// SSP clock always runs at 24MHz
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assign ssp_clk = pck0;
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// SSP frame is gated by clk_state and goes high when pck_divider=8..15
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assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;
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always @(posedge pck0)
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begin
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if(pck_divider == divisor[7:0])
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begin
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pck_divider <= 8'd0;
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clk_state = !clk_state;
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end
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else
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begin
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pck_divider <= pck_divider + 1;
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end
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end
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always @(posedge pck0)
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begin
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if((pck_divider == 8'd7) && !clk_state)
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begin
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to_arm_shiftreg <= adc_d;
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end
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else
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begin
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to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
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to_arm_shiftreg[0] <= 1'b0;
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end
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end
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endmodule
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