mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-21 15:56:21 +08:00
7bc95e2e43
- enhanced tracing: hf 14a list now shows meaningful timing information. With new option f it also shows the frame delay times (fdt) - small fix for hf 14b list - it used to run into the trace trailer - hf 14a sim now obeys iso14443 timing (fdt of 1172 or 1234 resp.) Note: you need to flash FPGA as well. More details in http://www.proxmark.org/forum/viewtopic.php?pid=9721#p9721
432 lines
14 KiB
Verilog
432 lines
14 KiB
Verilog
//-----------------------------------------------------------------------------
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// ISO14443-A support for the Proxmark III
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// Gerhard de Koning Gans, April 2008
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//-----------------------------------------------------------------------------
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// constants for the different modes:
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`define SNIFFER 3'b000
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`define TAGSIM_LISTEN 3'b001
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`define TAGSIM_MOD 3'b010
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`define READER_LISTEN 3'b011
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`define READER_MOD 3'b100
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module hi_iso14443a(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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mod_type
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input [2:0] mod_type;
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reg ssp_clk;
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reg ssp_frame;
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wire adc_clk;
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assign adc_clk = ck_1356meg;
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reg after_hysteresis, after_hysteresis_prev1, after_hysteresis_prev2, after_hysteresis_prev3, after_hysteresis_prev4;
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reg [11:0] has_been_low_for;
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reg [8:0] saw_deep_modulation;
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reg [2:0] deep_counter;
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reg deep_modulation;
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always @(negedge adc_clk)
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begin
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if(& adc_d[7:6]) after_hysteresis <= 1'b1; // adc_d >= 196 (U >= 3,28V) -> after_hysteris = 1
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else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0; // if adc_d <= 15 (U <= 1,13V) -> after_hysteresis = 0
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if(~(| adc_d[7:0])) // if adc_d == 0 (U <= 0,94V)
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begin
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if(deep_counter == 3'd7) // adc_d == 0 for 7 adc_clk ticks -> deep_modulation (by reader)
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begin
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deep_modulation <= 1'b1;
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saw_deep_modulation <= 8'd0;
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end
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else
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deep_counter <= deep_counter + 1;
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end
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else
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begin
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deep_counter <= 3'd0;
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if(saw_deep_modulation == 8'd255) // adc_d != 0 for 255 adc_clk ticks -> deep_modulation is over, now waiting for tag's response
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deep_modulation <= 1'b0;
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else
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saw_deep_modulation <= saw_deep_modulation + 1;
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end
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if(after_hysteresis)
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begin
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has_been_low_for <= 12'd0;
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end
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else
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begin
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if(has_been_low_for == 12'd4095)
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begin
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has_been_low_for <= 12'd0;
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after_hysteresis <= 1'b1; // reset after_hysteresis to 1 if it had been 0 for 4096 cycles (no field)
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end
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else
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begin
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has_been_low_for <= has_been_low_for + 1;
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end
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end
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end
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// Report every 4 subcarrier cycles
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// 128 periods of carrier frequency => 7-bit counter [negedge_cnt]
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reg [6:0] negedge_cnt;
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reg bit1, bit2, bit3, bit4;
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reg curbit;
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// storage for four previous samples:
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reg [7:0] adc_d_1;
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reg [7:0] adc_d_2;
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reg [7:0] adc_d_3;
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reg [7:0] adc_d_4;
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// the filtered signal (filter performs noise reduction and edge detection)
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// (gaussian derivative)
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wire signed [10:0] adc_d_filtered;
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assign adc_d_filtered = (adc_d_4 << 1) + adc_d_3 - adc_d_1 - (adc_d << 1);
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// Registers to store steepest edges detected:
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reg [7:0] rx_mod_falling_edge_max;
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reg [7:0] rx_mod_rising_edge_max;
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// A register to send 8 Bit results to the arm
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reg [7:0] to_arm;
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reg bit_to_arm;
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reg fdt_indicator, fdt_elapsed;
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reg [10:0] fdt_counter;
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//reg [47:0] mod_sig_buf;
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reg [31:0] mod_sig_buf;
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//reg [5:0] mod_sig_ptr;
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reg [4:0] mod_sig_ptr;
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reg [3:0] mod_sig_flip;
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reg mod_sig, mod_sig_coil;
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reg temp_buffer_reset;
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reg sendbit;
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reg [3:0] sub_carrier_cnt;
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// ADC data appears on the rising edge, so sample it on the falling edge
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always @(negedge adc_clk)
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begin
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// ------------------------------------------------------------------------------------------------------------------------------------------------------------------
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// relevant for TAGSIM_MOD only. Timing of Tag's answer relative to a command received from a reader
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// ISO14443-3 specifies:
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// fdt = 1172, if last bit was 0.
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// fdt = 1236, if last bit was 1.
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// the FPGA takes care for the 1172 delay. To achieve the additional 1236-1172=64 ticks delay, the ARM must send an additional correction bit (before the start bit).
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// The correction bit will be coded as 00010000, i.e. it adds 4 bits to the transmission stream, causing the required delay.
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if(fdt_counter == 11'd547) fdt_indicator <= 1'b1; // The ARM must not send earlier to prevent mod_sig_buf overflow.
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// The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks. fdt_indicator
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// could appear at ssp_din after 1 tick, 16 ticks for the transfer, 128 ticks until response is sended.
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// 1148 - 464 - 1 - 128 - 8 = 547
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if ((mod_type == `TAGSIM_MOD) || (mod_type == `TAGSIM_LISTEN))
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begin
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if(fdt_counter == 11'd1148) // the RF part delays the rising edge by approx 5 adc_clk_ticks, the ADC needs 3 clk_ticks for A/D conversion,
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// 16 ticks delay by mod_sig_buf
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// 1172 - 5 - 3 - 16 = 1148.
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begin
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if(fdt_elapsed)
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begin
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if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig; // start modulating (if mod_sig is already set)
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sub_carrier_cnt[3:0] <= sub_carrier_cnt[3:0] + 1;
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end
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else
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begin
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mod_sig_flip <= negedge_cnt[3:0]; // start modulation at this time
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sub_carrier_cnt[3:0] <= 0; // subcarrier phase in sync with start of modulation
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mod_sig_coil <= mod_sig; // assign signal to coil
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fdt_elapsed = 1'b1;
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if(~(| mod_sig_ptr[4:0])) mod_sig_ptr <= 5'd9; // if mod_sig_ptr == 0 -> didn't receive a 1 yet. Delay next 1 by n*128 ticks.
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else temp_buffer_reset = 1'b1; // else fix the buffer size at current position
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end
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end
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else
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begin
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fdt_counter <= fdt_counter + 1; // Count until 1155
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end
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end
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else // other modes: don't use the delay line.
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begin
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mod_sig_coil <= ssp_dout;
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end
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//-------------------------------------------------------------------------------------------------------------------------------------------
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// Relevant for READER_LISTEN only
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// look for steepest falling and rising edges:
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if(negedge_cnt[3:0] == 4'd1) // reset modulation detector. Save current edge.
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begin
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if (adc_d_filtered > 0)
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begin
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rx_mod_falling_edge_max <= adc_d_filtered;
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rx_mod_rising_edge_max <= 0;
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end
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else
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begin
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rx_mod_falling_edge_max <= 0;
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rx_mod_rising_edge_max <= -adc_d_filtered;
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end
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end
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else // detect modulation
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begin
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if (adc_d_filtered > 0)
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begin
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if (adc_d_filtered > rx_mod_falling_edge_max)
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rx_mod_falling_edge_max <= adc_d_filtered;
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end
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else
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begin
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if (-adc_d_filtered > rx_mod_rising_edge_max)
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rx_mod_rising_edge_max <= -adc_d_filtered;
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end
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end
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// detect modulation signal: if modulating, there must be a falling and a rising edge
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if (rx_mod_falling_edge_max > 6 && rx_mod_rising_edge_max > 6)
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curbit <= 1'b1; // modulation
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else
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curbit <= 1'b0; // no modulation
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// store previous samples for filtering and edge detection:
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adc_d_4 <= adc_d_3;
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adc_d_3 <= adc_d_2;
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adc_d_2 <= adc_d_1;
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adc_d_1 <= adc_d;
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// Relevant for TAGSIM_MOD only (timing the Tag's answer. See above)
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// When we see end of a modulation and we are emulating a Tag, start fdt_counter.
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// Reset fdt_counter when modulation is detected.
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if(~after_hysteresis /* && mod_sig_buf_empty */ && mod_type == `TAGSIM_LISTEN)
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begin
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fdt_counter <= 11'd0;
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fdt_elapsed = 1'b0;
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fdt_indicator <= 1'b0;
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temp_buffer_reset = 1'b0;
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mod_sig_ptr <= 5'b00000;
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mod_sig = 1'b0;
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end
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if(negedge_cnt[3:0] == 4'd1)
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begin
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// What do we communicate to the ARM
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if(mod_type == `TAGSIM_LISTEN)
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sendbit = after_hysteresis;
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else if(mod_type == `TAGSIM_MOD)
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/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
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else */
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sendbit = fdt_indicator;
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else if (mod_type == `READER_LISTEN)
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sendbit = curbit;
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else
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sendbit = 1'b0;
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end
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//------------------------------------------------------------------------------------------------------------------------------------------
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// Prepare 8 Bits to communicate to ARM
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// in SNIFFER mode: 4 Bits data sniffed as Tag, 4 Bits data sniffed as Reader
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if(mod_type == `SNIFFER)
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begin
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if (negedge_cnt == 7'd63)
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begin
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if(deep_modulation) // a reader is sending (or there's no field at all)
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begin
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to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis_prev4,1'b0,1'b0,1'b0,1'b0};
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end
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else
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begin
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to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis_prev4,bit1,bit2,bit3,bit4};
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end
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negedge_cnt <= 0;
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1;
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end
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end
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else
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// other modes: 8 Bits info on queue delay
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begin
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if(negedge_cnt == 7'd127)
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begin
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if (mod_type == `TAGSIM_MOD)
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begin
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to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]};
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end
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else
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begin
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to_arm[7:0] <= 8'd0;
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end
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negedge_cnt <= 0;
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1;
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end
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end
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if(negedge_cnt == 7'd1)
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begin
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after_hysteresis_prev1 <= after_hysteresis;
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bit1 <= curbit;
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end
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if(negedge_cnt == 7'd17)
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begin
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after_hysteresis_prev2 <= after_hysteresis;
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bit2 <= curbit;
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end
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if(negedge_cnt == 7'd33)
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begin
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after_hysteresis_prev3 <= after_hysteresis;
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bit3 <= curbit;
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end
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if(negedge_cnt == 7'd47)
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begin
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after_hysteresis_prev4 <= after_hysteresis;
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bit4 <= curbit;
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end
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//--------------------------------------------------------------------------------------------------------------------------------------------------------------
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// Relevant in TAGSIM_MOD only. Delay-Line to buffer data and send it at the correct time
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if(negedge_cnt[3:0] == 4'd0) // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
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begin
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mod_sig_buf[31:0] <= {mod_sig_buf[30:1], ssp_dout, 1'b0}; // shift in new data starting at mod_sig_buf[1]. mod_sig_buf[0] = 0 always.
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// asign the delayed signal to mod_sig, but don't modulate with the correction bit (which is sent as 00010000, all other bits will come with at least 2 consecutive 1s)
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// side effect: when ptr = 1 it will cancel the first 1 of every block of ones. Note: this would only be the case if we received a 1 just before fdt_elapsed.
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if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt_counter = 1148 adc_clk ticks.
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//if(mod_sig_ptr == 6'b101110) // buffer overflow at 46 - this would mean data loss
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//begin
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// mod_sig_ptr <= 6'b000000;
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//end
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if (mod_sig_ptr == 5'd30) mod_sig_ptr <= 5'd0;
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else mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). ptr always points to first 1.
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else if(fdt_elapsed && ~temp_buffer_reset)
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// fdt_elapsed. If we didn't receive a 1 yet, ptr will be at 9 and not yet fixed. Otherwise temp_buffer_reset will be 1 already.
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begin
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// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
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// at intervals of 8 * 16 = 128 adc_clk ticks intervals (as defined in ISO14443-3)
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if(ssp_dout) temp_buffer_reset = 1'b1;
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if(mod_sig_ptr == 5'd2) mod_sig_ptr <= 5'd9; // still nothing received, need to go for the next interval
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else mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
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end
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else
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begin
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if(~mod_sig_buf[mod_sig_ptr-1] && ~mod_sig_buf[mod_sig_ptr+1]) mod_sig = 1'b0;
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// finally, assign the delayed signal:
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else mod_sig = mod_sig_buf[mod_sig_ptr];
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end
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end
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//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
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// Communication to ARM (SSP Clock and data)
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// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
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if(mod_type == `SNIFFER)
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begin
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if(negedge_cnt[2:0] == 3'b100)
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ssp_clk <= 1'b0;
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if(negedge_cnt[2:0] == 3'b000)
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begin
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ssp_clk <= 1'b1;
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// Don't shift if we just loaded new data, obviously.
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if(negedge_cnt[5:0] != 6'd0)
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begin
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to_arm[7:1] <= to_arm[6:0];
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end
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end
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if(negedge_cnt[5:4] == 2'b00)
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ssp_frame = 1'b1;
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else
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ssp_frame = 1'b0;
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bit_to_arm = to_arm[7];
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end
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else
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//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
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// Communication to ARM (SSP Clock and data)
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// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
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begin
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if(negedge_cnt[3:0] == 4'b1000) ssp_clk <= 1'b0;
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if(negedge_cnt[3:0] == 4'b0111)
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begin
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// if(ssp_frame_counter == 3'd7) ssp_frame_counter <= 3'd0;
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// else ssp_frame_counter <= ssp_frame_counter + 1;
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if (negedge_cnt[6:4] == 3'b000) ssp_frame = 1'b1;
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else ssp_frame = 1'b0;
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end
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// ssp_frame = (ssp_frame_counter == 3'd7);
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if(negedge_cnt[3:0] == 4'b0000)
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begin
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ssp_clk <= 1'b1;
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// Don't shift if we just loaded new data, obviously.
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if(negedge_cnt[6:0] != 7'd0)
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begin
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to_arm[7:1] <= to_arm[6:0];
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end
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end
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if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
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// transmit timing information
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bit_to_arm = to_arm[7];
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else
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// transmit data or fdt_indicator
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bit_to_arm = sendbit;
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end
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end //always @(negedge adc_clk)
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assign ssp_din = bit_to_arm;
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// Subcarrier (adc_clk/16, for TAGSIM_MOD only).
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wire sub_carrier;
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assign sub_carrier = ~sub_carrier_cnt[3];
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// in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
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assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));
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// Enable HF antenna drivers:
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assign pwr_oe1 = 1'b0;
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assign pwr_oe3 = 1'b0;
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// TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
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// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
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// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
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assign pwr_oe4 = ~(mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD));
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// This is all LF, so doesn't matter.
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assign pwr_oe2 = 1'b0;
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assign pwr_lo = 1'b0;
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assign dbg = negedge_cnt[3];
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endmodule
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