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38d49097f9
switching Fpgamode while sniffing with FpgaWriteConfWord() was sometimes too long so the tag answer start was lost. Now, (only with FPGA_BITSTREAM_HF_15) with "FPGA_HF_READER_MODE_SNIFF_AMPLITUDE | FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ": the amplitude is shrank from its 2 LSB bits and those 2 bits are now used to return the current frequency. From my tests, this 2 bits reduction does not affect quality of 1SC sniffing, but it may have slightly reduced the receiving range. FPGA FSK decoding code is also improved.
148 lines
5.9 KiB
C
148 lines
5.9 KiB
C
//-----------------------------------------------------------------------------
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// Copyright (C) Jonathan Westhues, April 2006
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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// Routines to load the FPGA image, and then to configure the FPGA's major
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// mode once it is configured.
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//-----------------------------------------------------------------------------
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#ifndef __FPGALOADER_H
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#define __FPGALOADER_H
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#include "common.h"
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#define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
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#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
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// definitions for multiple FPGA config files support
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#define FPGA_BITSTREAM_LF 1
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#define FPGA_BITSTREAM_HF 2
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#define FPGA_BITSTREAM_HF_FELICA 3
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#define FPGA_BITSTREAM_HF_15 4
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/*
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Communication between ARM / FPGA is done inside armsrc/fpgaloader.c (function FpgaSendCommand)
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Send 16 bit command / data pair to FPGA
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The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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where
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C is 4bit command
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D is 12bit data
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-----+--------- frame layout --------------------
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bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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-----+-------------------------------------------
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cmd | x x x x
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major| x x x
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opt | x x
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divi | x x x x x x x x
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thres| x x x x x x x x
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-----+-------------------------------------------
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*/
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// Definitions for the FPGA commands.
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// BOTH HF / LF
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#define FPGA_CMD_SET_CONFREG (1<<12) // C
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// LF
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#define FPGA_CMD_SET_DIVISOR (2<<12) // C
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#define FPGA_CMD_SET_USER_BYTE1 (3<<12) // C
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// HF
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#define FPGA_CMD_TRACE_ENABLE (2<<12) // C
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// Definitions for the FPGA configuration word.
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#define FPGA_MAJOR_MODE_MASK 0x01C0
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#define FPGA_MINOR_MODE_MASK 0x003F
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// LF
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#define FPGA_MAJOR_MODE_LF_READER (0<<6)
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#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6)
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#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<6)
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#define FPGA_MAJOR_MODE_LF_ADC (3<<6)
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// HF
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#define FPGA_MAJOR_MODE_HF_READER (0<<6) // D
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#define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6) // D
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#define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6) // D
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#define FPGA_MAJOR_MODE_HF_SNIFF (3<<6) // D
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#define FPGA_MAJOR_MODE_HF_ISO18092 (4<<6) // D
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#define FPGA_MAJOR_MODE_HF_GET_TRACE (5<<6) // D
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#define FPGA_MAJOR_MODE_HF_FSK_READER (6<<6) // D
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// BOTH HF / LF
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#define FPGA_MAJOR_MODE_OFF (7<<6) // D
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// Options for LF_READER
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#define FPGA_LF_ADC_READER_FIELD 0x1
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// Options for LF_EDGE_DETECT
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1
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#define FPGA_LF_EDGE_DETECT_READER_FIELD 0x1
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#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 0x2
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// Options for the HF reader
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#define FPGA_HF_READER_MODE_RECEIVE_IQ (0<<0)
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#define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE (1<<0)
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#define FPGA_HF_READER_MODE_RECEIVE_PHASE (2<<0)
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#define FPGA_HF_READER_MODE_SEND_FULL_MOD (3<<0)
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#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD (4<<0)
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#define FPGA_HF_READER_MODE_SNIFF_IQ (5<<0)
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#define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE (6<<0)
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#define FPGA_HF_READER_MODE_SNIFF_PHASE (7<<0)
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#define FPGA_HF_READER_MODE_SEND_JAM (8<<0)
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#define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4)
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#define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4)
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#define FPGA_HF_READER_SUBCARRIER_212_KHZ (2<<4)
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#define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ (3<<4)
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// Options for the HF simulated tag, how to modulate
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#define FPGA_HF_SIMULATOR_NO_MODULATION 0x0 // 0000
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK 0x1 // 0001
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#define FPGA_HF_SIMULATOR_MODULATE_212K 0x2 // 0010
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#define FPGA_HF_SIMULATOR_MODULATE_424K 0x4 // 0100
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#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5 // 0101
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// no 848K
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// Options for ISO14443A
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#define FPGA_HF_ISO14443A_SNIFFER 0x0
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#define FPGA_HF_ISO14443A_TAGSIM_LISTEN 0x1
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#define FPGA_HF_ISO14443A_TAGSIM_MOD 0x2
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#define FPGA_HF_ISO14443A_READER_LISTEN 0x3
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#define FPGA_HF_ISO14443A_READER_MOD 0x4
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//options for Felica.
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#define FPGA_HF_ISO18092_FLAG_NOMOD 0x1 // 0001 disable modulation module
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#define FPGA_HF_ISO18092_FLAG_424K 0x2 // 0010 should enable 414k mode (untested). No autodetect
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#define FPGA_HF_ISO18092_FLAG_READER 0x4 // 0100 enables antenna power, to act as a reader instead of tag
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void FpgaSendCommand(uint16_t cmd, uint16_t v);
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void FpgaWriteConfWord(uint16_t v);
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void FpgaEnableTracing(void);
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void FpgaDisableTracing(void);
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void FpgaDownloadAndGo(int bitstream_version);
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// void FpgaGatherVersion(int bitstream_version, char *dst, int len);
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void FpgaSetupSsc(uint16_t fpga_mode);
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void SetupSpi(int mode);
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bool FpgaSetupSscDma(uint8_t *buf, uint16_t len);
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void Fpga_print_status(void);
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int FpgaGetCurrent(void);
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void SetAdcMuxFor(uint32_t whichGpio);
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// extern and generel turn off the antenna method
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void switch_off(void);
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#endif
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