mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-01-07 00:28:07 +08:00
8652988d62
Remove the now unnecessary files (merge-srec.pl, ldscript-ram-jtag) Note that this drops the dependency on perl for bootrom build, so end-users who don't touch the FPGA bitstream will not need perl anymore
43 lines
1.4 KiB
Text
43 lines
1.4 KiB
Text
MEMORY
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{
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/* AT91SAM7S256 has 256k Flash and 64k RAM */
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/* Important note: the correct ORIGIN for bootphase1 is 0x00100000 and for bootphase2 is 0x00100200
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However, this will confuse the currently deployed flash code which expects logical and and not
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physical addresses and performs no sanity checks at all. If confronted with physical addresses,
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it will happily erase everything and brick the device. So for the time being pretend these addresses
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to start at 0x0 while updating all the flash code with proper sanity checks, then come back later and
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fix the addresses. -- Henryk Plötz <henryk@ploetzli.ch> 2009-08-27 */
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bootphase1 : ORIGIN = 0x00000000, LENGTH = 0x200 /* Phase 1 bootloader: Copies real bootloader to RAM */
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bootphase2 : ORIGIN = 0x00000200, LENGTH = 0x2000 - 0x200 /* Main bootloader code, stored in Flash, executed from RAM */
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ram : ORIGIN = 0x00200000, LENGTH = 32K
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}
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SECTIONS
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{
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. = 0;
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bootphase1 : {
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*(.startup)
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*(.bootphase1)
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} >bootphase1
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bootphase2 : {
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__bootphase2_start__ = .;
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*(.startphase2)
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*(.text)
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*(.glue_7)
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*(.rodata)
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*(.data)
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. = ALIGN( 32 / 8 );
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__bootphase2_end__ = .;
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} >ram AT>bootphase2
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.bss : {
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__bss_start__ = .;
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*(.bss)
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} >ram
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. = ALIGN( 32 / 8 );
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__bss_end__ = .;
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}
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