mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-27 02:36:13 +08:00
6658905f18
It is identical to the popular 20081211, with the doob addition (20090301), a linux client, and two additional commands for LF analysis. Let me know if you find issues here!
103 lines
2.9 KiB
Verilog
103 lines
2.9 KiB
Verilog
//-----------------------------------------------------------------------------
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// The way that we connect things in low-frequency read mode. In this case
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// we are generating the 134 kHz or 125 kHz carrier, and running the
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// unmodulated carrier at that frequency. The A/D samples at that same rate,
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// and the result is serialized.
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module lo_read(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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lo_is_125khz
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input lo_is_125khz;
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// The low-frequency RFID stuff. This is relatively simple, because most
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// of the work happens on the ARM, and we just pass samples through. The
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// PCK0 must be divided down to generate the A/D clock, and from there by
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// a factor of 8 to generate the carrier (that we apply to the coil drivers).
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//
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// This is also where we decode the received synchronous serial port words,
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// to determine how to drive the output enables.
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// PCK0 will run at (PLL clock) / 4, or 24 MHz. That means that we can do
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// 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by
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// dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).
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reg [3:0] pck_divider;
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reg clk_lo;
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always @(posedge pck0)
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begin
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if(lo_is_125khz)
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begin
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if(pck_divider == 4'd11)
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begin
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pck_divider <= 4'd0;
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clk_lo = !clk_lo;
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end
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else
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pck_divider <= pck_divider + 1;
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end
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else
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begin
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if(pck_divider == 4'd10)
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begin
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pck_divider <= 4'd0;
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clk_lo = !clk_lo;
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end
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else
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pck_divider <= pck_divider + 1;
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end
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end
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reg [2:0] carrier_divider_lo;
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always @(posedge clk_lo)
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begin
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carrier_divider_lo <= carrier_divider_lo + 1;
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end
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assign pwr_lo = carrier_divider_lo[2];
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// This serializes the values returned from the A/D, and sends them out
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// over the SSP.
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reg [7:0] to_arm_shiftreg;
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always @(posedge clk_lo)
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begin
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if(carrier_divider_lo == 3'b000)
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to_arm_shiftreg <= adc_d;
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else
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to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
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end
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assign ssp_clk = clk_lo;
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assign ssp_frame = (carrier_divider_lo == 3'b001);
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assign ssp_din = to_arm_shiftreg[7];
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// The ADC converts on the falling edge, and our serializer loads when
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// carrier_divider_lo == 3'b000.
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assign adc_clk = ~carrier_divider_lo[2];
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assign pwr_hi = 1'b0;
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assign dbg = adc_clk;
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endmodule
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