mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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106 lines
4.7 KiB
Verilog
106 lines
4.7 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The FPGA is responsible for interfacing between the A/D, the coil drivers,
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// and the ARM. In the low-frequency modes it passes the data straight
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// through, so that the ARM gets raw A/D samples over the SSP. In the high-
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// frequency modes, the FPGA might perform some demodulation first, to
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// reduce the amount of data that we must send to the ARM.
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//-----------------------------------------------------------------------------
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//`include "fpga_lf.v"
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//`include "fpga_hf.v"
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//`include "mux2_onein.v"
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//`include "mux2_oneout.v"
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//`include "util.v"
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module fpga_top(
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input spck,
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output miso,
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input mosi,
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input ncs,
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input pck0,
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input ck_1356meg,
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input ck_1356megb,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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input [7:0] adc_d,
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output adc_clk,
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output adc_noe,
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output ssp_frame,
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output ssp_din,
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input ssp_dout,
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output ssp_clk,
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input cross_hi,
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input cross_lo,
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output dbg,
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output PWR_LO_EN,
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input FPGA_SWITCH
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);
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fpga_hf hfmod(
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hfspck, hfmiso, hfmosi, hfncs,
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hfpck0, hfck_1356meg, hfck_1356megb,
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hfpwr_lo, hfpwr_hi,
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hfpwr_oe1, hfpwr_oe2, hfpwr_oe3, hfpwr_oe4,
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adc_d, hfadc_clk, hfadc_noe,
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hfssp_frame, hfssp_din, hfssp_dout, hfssp_clk,
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hfcross_hi, hfcross_lo,
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hfdebug
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);
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fpga_lf lfmod(
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lfspck, lfmiso, lfmosi, lfncs,
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lfpck0, lfck_1356meg, lfck_1356megb,
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lfpwr_lo, lfpwr_hi,
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lfpwr_oe1, lfpwr_oe2, lfpwr_oe3, lfpwr_oe4,
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adc_d, lfadc_clk, lfadc_noe,
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lfssp_frame, lfssp_din, lfssp_dout, lfssp_clk,
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lfcross_hi, lfcross_lo,
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lfdebug,
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lfPWR_LO_EN
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);
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mux2_oneout mux_spck_all (FPGA_SWITCH, spck, hfspck, lfspck);
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mux2_one mux_miso_all (FPGA_SWITCH, miso, hfmiso, lfmiso);
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mux2_oneout mux_mosi_all (FPGA_SWITCH, mosi, hfmosi, lfmosi);
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mux2_oneout mux_ncs_all (FPGA_SWITCH, ncs, hfncs, lfncs);
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mux2_oneout mux_pck0_all (FPGA_SWITCH, pck0, hfpck0, lfpck0);
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mux2_oneout mux_ck_1356meg_all (FPGA_SWITCH, ck_1356meg, hfck_1356meg, lfck_1356meg);
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mux2_oneout mux_ck_1356megb_all (FPGA_SWITCH, ck_1356megb, hfck_1356megb, lfck_1356megb);
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mux2_one mux_pwr_lo_all (FPGA_SWITCH, pwr_lo, hfpwr_lo, lfpwr_lo);
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mux2_one mux_pwr_hi_all (FPGA_SWITCH, pwr_hi, hfpwr_hi, lfpwr_hi);
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mux2_one mux_pwr_oe1_all (FPGA_SWITCH, pwr_oe1, hfpwr_oe1, lfpwr_oe1);
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mux2_one mux_pwr_oe2_all (FPGA_SWITCH, pwr_oe2, hfpwr_oe2, lfpwr_oe2);
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mux2_one mux_pwr_oe3_all (FPGA_SWITCH, pwr_oe3, hfpwr_oe3, lfpwr_oe3);
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mux2_one mux_pwr_oe4_all (FPGA_SWITCH, pwr_oe4, hfpwr_oe4, lfpwr_oe4);
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mux2_one mux_adc_clk_all (FPGA_SWITCH, adc_clk, hfadc_clk, lfadc_clk);
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mux2_one mux_adc_noe_all (FPGA_SWITCH, adc_noe, adc_noe, lfadc_noe);
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mux2_one mux_ssp_frame_all (FPGA_SWITCH, ssp_frame, hfssp_frame, lfssp_frame);
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mux2_one mux_ssp_din_all (FPGA_SWITCH, ssp_din, hfssp_din, lfssp_din);
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mux2_oneout mux_ssp_dout_all (FPGA_SWITCH, ssp_dout, hfssp_dout, lfssp_dout);
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mux2_one mux_ssp_clk_all (FPGA_SWITCH, ssp_clk, hfssp_clk, lfssp_clk);
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mux2_oneout mux_cross_hi_all (FPGA_SWITCH, cross_hi, hfcross_hi, lfcross_hi);
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mux2_oneout mux_cross_lo_all (FPGA_SWITCH, cross_lo, hfcross_lo, lfcross_lo);
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mux2_one mux_dbg_all (FPGA_SWITCH, dbg, hfdebug, lfdebug);
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mux2_one mux_PWR_LO_EN_all (FPGA_SWITCH, PWR_LO_EN, 1'b0, lfPWR_LO_EN);
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endmodule
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