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234 lines
9.3 KiB
Verilog
234 lines
9.3 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The FPGA is responsible for interfacing between the A/D, the coil drivers,
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// and the ARM. In the low-frequency modes it passes the data straight
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// through, so that the ARM gets raw A/D samples over the SSP. In the high-
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// frequency modes, the FPGA might perform some demodulation first, to
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// reduce the amount of data that we must send to the ARM.
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//-----------------------------------------------------------------------------
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// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
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// Note: the definitions here are without shifts
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// Commands:
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`define FPGA_CMD_SET_CONFREG 1
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`define FPGA_CMD_TRACE_ENABLE 2
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// Major modes:
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`define FPGA_MAJOR_MODE_HF_READER 0
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`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
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`define FPGA_MAJOR_MODE_HF_ISO14443A 2
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`define FPGA_MAJOR_MODE_HF_SNIFF 3
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`define FPGA_MAJOR_MODE_HF_ISO18092 4
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`define FPGA_MAJOR_MODE_HF_GET_TRACE 5
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`define FPGA_MAJOR_MODE_HF_FSK_READER 6
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`define FPGA_MAJOR_MODE_OFF 7
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// Options for the generic HF reader
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`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
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`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
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`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
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`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
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`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
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`define FPGA_HF_READER_MODE_SNIFF_IQ 5
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`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
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`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
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`define FPGA_HF_READER_MODE_SEND_JAM 8
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`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
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`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
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`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
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`define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ 3
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`define FPGA_HF_FSK_READER_OUTPUT_1695_KHZ 0
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`define FPGA_HF_FSK_READER_OUTPUT_848_KHZ 1
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`define FPGA_HF_FSK_READER_OUTPUT_424_KHZ 2
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`define FPGA_HF_FSK_READER_OUTPUT_212_KHZ 3
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`define FPGA_HF_FSK_READER_NOPOWER 0
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`define FPGA_HF_FSK_READER_WITHPOWER 1
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// Options for the HF simulated tag, how to modulate
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`define FPGA_HF_SIMULATOR_NO_MODULATION 0
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`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
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`define FPGA_HF_SIMULATOR_MODULATE_212K 2
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`define FPGA_HF_SIMULATOR_MODULATE_424K 4
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`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
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// Options for ISO14443A
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`define FPGA_HF_ISO14443A_SNIFFER 0
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`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
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`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
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`define FPGA_HF_ISO14443A_READER_LISTEN 3
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`define FPGA_HF_ISO14443A_READER_MOD 4
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//options for ISO18092 / Felica
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`define FPGA_HF_ISO18092_FLAG_NOMOD 1 // 0001 disable modulation module
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`define FPGA_HF_ISO18092_FLAG_424K 2 // 0010 should enable 414k mode (untested). No autodetect
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`define FPGA_HF_ISO18092_FLAG_READER 4 // 0100 enables antenna power, to act as a reader instead of tag
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`include "hi_reader_15.v"
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`include "hi_simulate.v"
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`include "hi_sniffer.v"
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`include "util.v"
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`include "hi_get_trace.v"
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module fpga_hf_15(
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input spck, output miso, input mosi, input ncs,
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input pck0, input ck_1356meg, input ck_1356megb,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk, output adc_noe,
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output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
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input cross_hi, input cross_lo,
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output dbg
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);
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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/*
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Attempt to write up how its hooked up.
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/ Iceman, 2020
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Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
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Send 16 bit command / data pair to FPGA
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The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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where
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C is 4bit command
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D is 12bit data
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shift_reg receive this 16bit frame
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-----+--------- frame layout --------------------
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bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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-----+-------------------------------------------
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cmd | x x x x
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major| x x x
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opt | x x x x
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sub | x x
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divi | x x x x x x x x
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thres| x x x x x x x x
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-----+-------------------------------------------
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*/
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reg [15:0] shift_reg;
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reg [8:0] conf_word;
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reg trace_enable;
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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// from it, which means that we must make sure that we can do so without
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// glitching, or else we will glitch the transmitted carrier.
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
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`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
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endcase
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end
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always @(posedge spck)
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begin
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if(~ncs)
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begin
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shift_reg[15:1] <= shift_reg[14:0];
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shift_reg[0] <= mosi;
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end
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end
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// select module (outputs) based on major mode
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wire [2:0] major_mode = conf_word[8:6];
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// configuring the HF reader
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wire [1:0] subcarrier_frequency = conf_word[5:4];
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wire [3:0] minor_mode = conf_word[3:0];
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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// 000 - HF 15 reader
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hi_15_reader hr(
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ck_1356megb,
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hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
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adc_d, hr_adc_clk,
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hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
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hr_dbg,
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subcarrier_frequency, minor_mode
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);
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// 001 - HF simulated tag
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hi_simulate hs(
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ck_1356meg,
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hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
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adc_d, hs_adc_clk,
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hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
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hs_dbg,
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minor_mode
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);
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// 011 - HF sniff
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hi_sniffer he(
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ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, he_ssp_clk
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);
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// 101 - HF get trace
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hi_get_trace gt(
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ck_1356megb,
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adc_d, trace_enable, major_mode,
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gt_ssp_frame, gt_ssp_din, gt_ssp_clk
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);
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// Major modes:
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// 000 -- HF 15 reader; subcarrier frequency and modulation depth selectable
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// 001 -- HF simulated tag
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// 010 --
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// 011 -- HF sniff
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// 100 --
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// 101 -- HF get trace
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// 110 -- unused
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// 111 -- FPGA_MAJOR_MODE_OFF
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// 000 001 010 011 100 101 110 111
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mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, 1'b0, he_ssp_clk, 1'b0, gt_ssp_clk, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, 1'b0, he_ssp_din, 1'b0, gt_ssp_din, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, 1'b0, he_ssp_frame, 1'b0, gt_ssp_frame, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, 1'b0, he_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, 1'b0, he_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, 1'b0, he_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, 1'b0, he_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, 1'b0, he_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, 1'b0, he_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, 1'b0, he_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, 1'b0, he_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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endmodule
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