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236 lines
8.6 KiB
Verilog
236 lines
8.6 KiB
Verilog
//-----------------------------------------------------------------------------
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// Jonathan Westhues, March 2006
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// iZsh <izsh at fail0verflow.com>, June 2014
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// Piwi, Feb 2019
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// Anon, 2019
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//-----------------------------------------------------------------------------
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// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
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// Note: the definitions here are without shifts
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// Commands:
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`define FPGA_CMD_SET_CONFREG 1
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`define FPGA_CMD_SET_DIVISOR 2
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`define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD 3
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// Major modes:
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`define FPGA_MAJOR_MODE_LF_READER 0
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`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
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`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
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`define FPGA_MAJOR_MODE_LF_ADC 3
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// Options for LF_READER
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`define FPGA_LF_ADC_READER_FIELD 1
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// Options for LF_EDGE_DETECT
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`define FPGA_LF_EDGE_DETECT_READER_FIELD 1
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`define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 2
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//For ISE 10.1 PROJ,IDE auto include
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//`include "lo_read.v"
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//`include "lo_passthru.v"
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//`include "lo_edge_detect.v"
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//`include "lo_adc.v"
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//`include "util.v"
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//`include "clk_divider.v"
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module fpga_lfmod(
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input spck, output miso, input mosi, input ncs,
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input pck0, input ck_1356meg, input ck_1356megb,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk, output adc_noe,
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output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
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input cross_hi, input cross_lo,
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output dbg,
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output PWR_LO_EN
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);
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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/*
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Attempt to write up how its hooked up. Iceman 2020.
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Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
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Send 16 bit command / data pair to FPGA
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The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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where
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C is 4bit command
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D is 12bit data
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shift_reg receive this 16bit frame
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LF command
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----------
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shift_reg[15:12] == 4bit command
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LF has three commands (FPGA_CMD_SET_CONFREG, FPGA_CMD_SET_DIVISOR, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD)
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Current commands uses only 2bits. We have room for up to 4bits of commands total (7).
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LF data
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-------
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shift_reg[11:0] == 12bit data
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lf data is divided into MAJOR MODES and configuration values.
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The major modes uses 3bits (0,1,2,3,7 | 000, 001, 010, 011, 111)
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000 FPGA_MAJOR_MODE_LF_READER = Act as LF reader (modulate)
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001 FPGA_MAJOR_MODE_LF_EDGE_DETECT = Simulate LF
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010 FPGA_MAJOR_MODE_LF_PASSTHRU = Passthrough mode, CROSS_LO line connected to SSP_DIN. SSP_DOUT logic level controls if we modulate / listening
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011 FPGA_MAJOR_MODE_LF_ADC = refactor hitag2, clear ADC sampling
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111 FPGA_MAJOR_MODE_OFF = turn off sampling.
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Each one of this major modes can have options. Currently these two major modes uses options.
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- FPGA_MAJOR_MODE_LF_READER
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- FPGA_MAJOR_MODE_LF_EDGE_DETECT
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FPGA_MAJOR_MODE_LF_READER
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-------------------------------------
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lf_field = 1bit (FPGA_LF_ADC_READER_FIELD)
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You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at
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divisor = 8bits shift_reg[7:0]
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FPGA_MAJOR_MODE_LF_EDGE_DETECT
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------------------------------------------
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lf_ed_toggle_mode = 1bits
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lf_ed_threshold = 8bits threshold defaults to 127
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You can send FPGA_CMD_SET_EDGE_DETECT_THRESHOLD to set a custom threshold
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lf_ed_threshold = 8bits threshold value.
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conf_word 12bits
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conf_word[7:5] = 3bit major mode.
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conf_word[0] = 1bit lf_field
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conf_word[1] = 1bit lf_ed_toggle_mode
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conf_word[7:0] = 8bit divisor
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conf_word[7:0] = 8bit threshold
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-----+--------- frame layout --------------------
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bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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-----+-------------------------------------------
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cmd | x x x x
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major| x x x
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opt | x x
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divi | x x x x x x x x
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thres| x x x x x x x x
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-----+-------------------------------------------
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*/
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reg [15:0] shift_reg;
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reg [7:0] divisor;
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reg [7:0] lf_ed_threshold;
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reg [11:0] conf_word;
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wire [2:0] major_mode = conf_word[8:6];
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wire lf_field = conf_word[0];
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wire lf_ed_toggle_mode = conf_word[1];
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// Handles cmd / data frame from ARM
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always @(posedge ncs)
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begin
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// 4 bit command
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case (shift_reg[15:12])
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`FPGA_CMD_SET_CONFREG:
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begin
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// 12 bit data
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conf_word <= shift_reg[11:0];
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if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
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begin
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lf_ed_threshold <= 127; // default threshold
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end
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end
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`FPGA_CMD_SET_DIVISOR:
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divisor <= shift_reg[7:0]; // 8bits
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`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
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lf_ed_threshold <= shift_reg[7:0]; // 8 bits
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endcase
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end
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// Receive 16bits of data from ARM here.
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always @(posedge spck)
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begin
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if (~ncs)
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begin
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shift_reg[15:1] <= shift_reg[14:0];
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shift_reg[0] <= mosi;
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end
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end
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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wire [7:0] pck_cnt;
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wire pck_divclk;
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clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
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lo_read lr(
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pck0, pck_cnt, pck_divclk,
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lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
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adc_d, lr_adc_clk,
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lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
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lr_dbg, lf_field
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);
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lo_passthru lp(
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pck_divclk,
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lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
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lp_adc_clk,
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lp_ssp_din, ssp_dout,
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cross_lo,
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lp_dbg
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);
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lo_edge_detect le(
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pck0, pck_divclk,
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le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
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adc_d, le_adc_clk,
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le_ssp_frame, ssp_dout, le_ssp_clk,
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cross_lo,
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le_dbg,
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lf_field,
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lf_ed_toggle_mode, lf_ed_threshold
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);
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lo_adc la(
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pck0,
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la_pwr_lo, la_pwr_hi, la_pwr_oe1, la_pwr_oe2, la_pwr_oe3, la_pwr_oe4,
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adc_d, la_adc_clk,
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la_ssp_frame, la_ssp_din, ssp_dout, la_ssp_clk,
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la_dbg, divisor,
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lf_field
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);
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// Major modes:
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// 000 -- LF reader (generic)
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// 001 -- LF edge detect (generic)
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// 010 -- LF passthrough
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// 011 -- LF ADC (read/write)
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// 100 -- unused
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// 101 -- unused
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// 110 -- unused
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// 111 -- FPGA_MAJOR_MODE_OFF
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// 000 001 010 011 100 101 110 111
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mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, la_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, la_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, la_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, la_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, la_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, la_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, la_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, la_pwr_lo, 1'b0, 1'b0, 1'b1, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, la_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, la_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, la_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ant (major_mode, PWR_LO_EN, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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endmodule
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