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66b1758278
Include statements in individual files are not required when compiling the code the correct way as a project with an explicitly defined work library. The Makefile exactly replicates the compilation process of the ISE environment and generates the required project files.
48 lines
1.4 KiB
Verilog
48 lines
1.4 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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// 16 inputs to 1 output multiplexer
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module mux16(
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input [3:0] sel,
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output reg y,
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input x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15
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);
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always @(*)
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begin
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// y = x[sel];
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case (sel)
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4'd0: y = x0;
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4'd1: y = x1;
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4'd2: y = x2;
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4'd3: y = x3;
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4'd4: y = x4;
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4'd5: y = x5;
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4'd6: y = x6;
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4'd7: y = x7;
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4'd8: y = x8;
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4'd9: y = x9;
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4'd10: y = x10;
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4'd11: y = x11;
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4'd12: y = x12;
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4'd13: y = x13;
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4'd14: y = x14;
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4'd15: y = x15;
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endcase
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end
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endmodule
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