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111 lines
3.1 KiB
Verilog
111 lines
3.1 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// testbench for lf_edge_detect
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`include "lf_edge_detect.v"
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`define FIN "tb_tmp/data.filtered.gold"
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`define FOUT_MIN "tb_tmp/data.min"
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`define FOUT_MAX "tb_tmp/data.max"
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`define FOUT_STATE "tb_tmp/data.state"
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`define FOUT_TOGGLE "tb_tmp/data.toggle"
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`define FOUT_HIGH "tb_tmp/data.high"
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`define FOUT_HIGHZ "tb_tmp/data.highz"
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`define FOUT_LOWZ "tb_tmp/data.lowz"
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`define FOUT_LOW "tb_tmp/data.low"
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module lf_edge_detect_tb;
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integer fin, fout_state, fout_toggle;
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integer fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
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integer r;
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reg clk = 0;
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reg [7:0] adc_d;
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wire adc_clk;
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wire data_rdy;
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wire edge_state;
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wire edge_toggle;
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wire [7:0] high_threshold;
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wire [7:0] highz_threshold;
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wire [7:0] lowz_threshold;
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wire [7:0] low_threshold;
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wire [7:0] max;
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wire [7:0] min;
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initial
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begin
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clk = 0;
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fin = $fopen(`FIN, "r");
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if (!fin) begin
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$display("ERROR: can't open the data file");
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$finish;
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end
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fout_min = $fopen(`FOUT_MIN, "w+");
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fout_max = $fopen(`FOUT_MAX, "w+");
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fout_state = $fopen(`FOUT_STATE, "w+");
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fout_toggle = $fopen(`FOUT_TOGGLE, "w+");
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fout_high = $fopen(`FOUT_HIGH, "w+");
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fout_highz = $fopen(`FOUT_HIGHZ, "w+");
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fout_lowz = $fopen(`FOUT_LOWZ, "w+");
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fout_low = $fopen(`FOUT_LOW, "w+");
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if (!$feof(fin))
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adc_d = $fgetc(fin); // read the first value
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end
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always
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# 1 clk = !clk;
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// input
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initial
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begin
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while (!$feof(fin)) begin
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@(negedge clk) adc_d <= $fgetc(fin);
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end
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if ($feof(fin))
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begin
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# 3 $fclose(fin);
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$fclose(fout_state);
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$fclose(fout_toggle);
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$fclose(fout_high);
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$fclose(fout_highz);
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$fclose(fout_lowz);
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$fclose(fout_low);
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$fclose(fout_min);
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$fclose(fout_max);
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$finish;
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end
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end
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initial
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begin
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// $monitor("%d\t S: %b, E: %b", $time, edge_state, edge_toggle);
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end
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// output
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always @(negedge clk)
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if ($time > 2) begin
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r = $fputc(min, fout_min);
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r = $fputc(max, fout_max);
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r = $fputc(edge_state, fout_state);
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r = $fputc(edge_toggle, fout_toggle);
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r = $fputc(high_threshold, fout_high);
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r = $fputc(highz_threshold, fout_highz);
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r = $fputc(lowz_threshold, fout_lowz);
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r = $fputc(low_threshold, fout_low);
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end
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// module to test
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lf_edge_detect detect(clk, adc_d, 8'd127,
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max, min,
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high_threshold, highz_threshold,
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lowz_threshold, low_threshold,
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edge_state, edge_toggle);
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endmodule
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