mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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c41c685807
hi_reader_15 was a superset of hi_reader, now uses conditional compile from Makefile like the other files to select compilations options
226 lines
7.7 KiB
Makefile
226 lines
7.7 KiB
Makefile
#
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# FPGA Makefile for all targets
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#
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# The top part of this Makefile is used to define custom options for a number of compilation targets
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# To define an additional target simply look at the other defined targets and add a new TARGET entry with a unique number and the custom options required
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XILINX_TOOLS_PREFIX=
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# Copy update (only when destination is older or missing)
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CP = cp -u
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# Make directory, no error if already existing
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MKDIR = mkdir -p
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# Remove recursive, force
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RMDIR = rm -rf
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# Path to make
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MAKE = make
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# Custom prefix for build directories, each target is built into its own separate directory name formed by combining the PREFIX and TARGET names.
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# This way the source is not polluted with build files and the build directories are left behind after compilation so logs and reports can be
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# examined or can be easily deleted with "make clean"
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PREFIX = __
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# Options to be passed to XST
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XST_OPTS_BASE = run
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XST_OPTS_BASE += -ifn xst.prj
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XST_OPTS_BASE += -ifmt mixed
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XST_OPTS_BASE += -ofmt NGC
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XST_OPTS_BASE += -lso xst.lso
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XST_OPTS_BASE += -top fpga_top
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XST_OPTS_BASE += -resource_sharing yes
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# Optimizations for speed (default)
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XST_OPTS_SPEED = -opt_mode Speed
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XST_OPTS_SPEED += -opt_level 1
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XST_OPTS_SPEED += -fsm_style lut
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XST_OPTS_SPEED += -fsm_encoding auto
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# Optimization for reduced space
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XST_OPTS_AREA = -opt_mode area
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XST_OPTS_AREA += -opt_level 2
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XST_OPTS_AREA += -fsm_style bram
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XST_OPTS_AREA += -fsm_encoding compact
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# Types of selective module compilation:
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# WITH_LF Enables selection of LF modules (and disables all HF)
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# To enable these modules WITH_LF _MUST_ be defined
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# WITH_LF0 enable LF reader (generic)
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# WITH_LF1 enable LF edge detect (generic)
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# WITH_LF2 enable LF passthrough
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# WITH_LF3 enable LF ADC (read/write)
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# To enable these modules WITH_LF _MUST_NOT_ be defined
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# WITH_HF0 enable HF reader (see also WITH_HF_15 below)
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# WITH_HF_15 select "iso15 2sc mode" extensions instead of original
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# WITH_HF1 enable HF simulated tag
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# WITH_HF2 enable HF ISO14443-A
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# WITH_HF3 enable sniff
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# WITH_HF4 enable HF ISO18092 FeliCa
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# WITH_HF5 enable HF get trace
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# RDV40/Generic - Enable LF and all the LF modules
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TARGET1_OPTIONS = -define \{WITH_LF WITH_LF0 WITH_LF1 WITH_LF2 WITH_LF3\}
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# RDV40/Generic - Enable all HF modules except Felica
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TARGET2_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF2 WITH_HF3 WITH_HF5\}
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# RDV40/Generic - Enable all HF modules except Felica and ISO14443, select HF_15 instead of HF
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TARGET3_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF3 WITH_HF5 WITH_HF_15\}
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# RDV40/Generic - Enable all HF modules except ISO14443
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TARGET4_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF3 WITH_HF4 WITH_HF5\}
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# ICOPYX
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TARGET5_OPTIONS = -define {PM3ICOPYX} -rtlview Yes
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# Here we list the target names
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TARGET1_NAME = fpga_pm3_lf
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TARGET2_NAME = fpga_pm3_hf
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TARGET3_NAME = fpga_pm3_hf_15
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TARGET4_NAME = fpga_pm3_felica
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TARGET5_NAME = fpga_icopyx_hf
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# Targets can be compiled for different FPGA flavours
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TARGET1_FPGA = xc2s30-5-vq100
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TARGET2_FPGA = $(TARGET1_FPGA)
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TARGET3_FPGA = $(TARGET1_FPGA)
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TARGET4_FPGA = $(TARGET1_FPGA)
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TARGET5_FPGA = xc3s100e-4-vq100
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# Assemble the final XST options for each target
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TARGET1_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA) -p $(TARGET1_FPGA) -ofn $(TARGET1_NAME) $(TARGET1_OPTIONS)
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TARGET2_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA) -p $(TARGET2_FPGA) -ofn $(TARGET2_NAME) $(TARGET2_OPTIONS)
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TARGET3_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA) -p $(TARGET3_FPGA) -ofn $(TARGET3_NAME) $(TARGET3_OPTIONS)
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TARGET4_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA) -p $(TARGET4_FPGA) -ofn $(TARGET4_NAME) $(TARGET4_OPTIONS)
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TARGET5_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_SPEED) -p $(TARGET5_FPGA) -ofn $(TARGET5_NAME) $(TARGET5_OPTIONS)
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# these files are common for all targets
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TARGET_COMMON_FILES = define.v
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TARGET_COMMON_FILES += mux8.v
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TARGET_COMMON_FILES += clk_divider.v
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TARGET_COMMON_FILES += lp20khz_1MSa_iir_filter.v
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TARGET_COMMON_FILES += min_max_tracker.v
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TARGET_COMMON_FILES += hi_flite.v
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TARGET_COMMON_FILES += hi_get_trace.v
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TARGET_COMMON_FILES += hi_iso14443a.v
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TARGET_COMMON_FILES += hi_reader.v
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TARGET_COMMON_FILES += hi_simulate.v
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TARGET_COMMON_FILES += hi_sniffer.v
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TARGET_COMMON_FILES += lf_edge_detect.v
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TARGET_COMMON_FILES += lo_adc.v
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TARGET_COMMON_FILES += lo_edge_detect.v
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TARGET_COMMON_FILES += lo_passthru.v
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TARGET_COMMON_FILES += lo_read.v
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# Add the files that are unique per target and all the common files
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TARGET1_FILES = $(TARGET_COMMON_FILES) fpga_pm3_top.v
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TARGET2_FILES = $(TARGET1_FILES)
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TARGET3_FILES = $(TARGET1_FILES)
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TARGET4_FILES = $(TARGET1_FILES)
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TARGET5_FILES = $(TARGET_COMMON_FILES) mux2_onein.v mux2_oneout.v fpga_icopyx_hf.v fpga_icopyx_lf.v fpga_icopyx_top.v
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# List of all valid target FPGA images to build
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TARGETS = $(TARGET1_NAME) $(TARGET2_NAME) $(TARGET3_NAME) $(TARGET4_NAME) $(TARGET5_NAME)
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# Verbosity type for ISE tools ise|xflow|silent
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VERBOSITY = -intstyle silent
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# Echo (Q=) or not echo (Q=@) build commands to the terminal
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Q=@
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# Pass the custom variables to the lower make rules
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$(TARGET1_NAME).bit: TARGET_FPGA = $(TARGET1_FPGA)
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$(TARGET1_NAME).bit: TARGET_FILES = $(TARGET1_FILES)
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$(TARGET1_NAME).bit: TARGET_XST_OPTS = $(TARGET1_XST_OPTS)
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$(TARGET2_NAME).bit: TARGET_FPGA = $(TARGET2_FPGA)
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$(TARGET2_NAME).bit: TARGET_FILES = $(TARGET2_FILES)
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$(TARGET2_NAME).bit: TARGET_XST_OPTS = $(TARGET2_XST_OPTS)
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$(TARGET3_NAME).bit: TARGET_FPGA = $(TARGET3_FPGA)
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$(TARGET3_NAME).bit: TARGET_FILES = $(TARGET3_FILES)
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$(TARGET3_NAME).bit: TARGET_XST_OPTS = $(TARGET3_XST_OPTS)
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$(TARGET4_NAME).bit: TARGET_FPGA = $(TARGET4_FPGA)
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$(TARGET4_NAME).bit: TARGET_FILES = $(TARGET4_FILES)
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$(TARGET4_NAME).bit: TARGET_XST_OPTS = $(TARGET4_XST_OPTS)
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$(TARGET5_NAME).bit: TARGET_FPGA = $(TARGET5_FPGA)
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$(TARGET5_NAME).bit: TARGET_FILES = $(TARGET5_FILES)
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$(TARGET5_NAME).bit: TARGET_XST_OPTS = $(TARGET5_XST_OPTS)
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$(TARGETS):
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$(Q)$(MKDIR) $(PREFIX)build_$@
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$(Q)$(MAKE) -C $(PREFIX)build_$@ -f ../Makefile $(notdir $@).bit
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work:
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$(Q)$(RM) xst.prj
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$(Q)for item in $(TARGET_FILES); do echo verilog work ../$$item>>xst.prj; done
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$(Q)echo work> xst.lso
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%.xst: work
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$(Q)$(RM) $@
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$(Q)echo $(TARGET_XST_OPTS)> $@
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%.ngc: %.xst
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$(Q)$(RM) $@
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$(info [-] XST $@)
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$(Q)$(XILINX_TOOLS_PREFIX)xst $(VERBOSITY) -ifn $<
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%.ngd: %.ngc
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$(Q)$(RM) $@
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$(info [-] NGD $@)
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$(Q)$(XILINX_TOOLS_PREFIX)ngdbuild $(VERBOSITY) -quiet -p $(TARGET_FPGA) -nt timestamp -uc ../$(TARGET_FPGA).ucf $< $@
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%_map.ncd: %.ngd
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$(Q)$(RM) $@
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$(info [-] MAP $@)
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$(Q)$(XILINX_TOOLS_PREFIX)map $(VERBOSITY) -p $(TARGET_FPGA) -o $*_map $*
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%.ncd: %_map.ncd
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$(Q)$(RM) $@
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$(info [-] PAR $@)
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$(Q)$(XILINX_TOOLS_PREFIX)par $(VERBOSITY) -w $< $@
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%.bit: %.ncd
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# Hacky hack, make empty files for icopyx
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if echo "$@" | grep -qi "icopyx"; then \
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truncate -s0 ../fpga_icopyx_lf.bit; \
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truncate -s0 ../fpga_icopyx_hf_15.bit; \
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truncate -s0 ../fpga_icopyx_felica.bit; \
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fi
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$(Q)$(RM) $@ $*.drc $*.rbt
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$(info [=] BITGEN $@)
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$(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
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$(Q)$(CP) $@ ..
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# Build all targets
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all: $(TARGETS)
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# ALWAYS have some hardcoded text after $(PREFIX) to avoid rm -rf * or rm -rf /* situations if PREFIX is incorrectly set to empty "" or just "/"
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clean:
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$(Q)$(RMDIR) $(PREFIX)build_*
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$(info [-] Build files deleted)
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.DEFAULT:
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@if [ "$@" != "all" ] && [ ! "$(filter $@,$(TARGETS))" ]; then \
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make help; \
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else \
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make all; \
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fi
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.PHONY: all help clean
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help:
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@echo "################################################################"
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@echo "#"
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@echo "# <target> - Builds only one of the above listed targets"
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@echo "# all - Builds the FPGA bitstreams for all targets"
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@echo "# clean - Keeps .bit files but cleans intermediate build files for all targets"
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@echo "#"
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@echo "#"
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@echo "# Valid targets are:"
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@echo "# $(TARGETS)"
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@echo "#"
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@echo "################################################################"
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