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96 lines
3.3 KiB
Verilog
96 lines
3.3 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The way that we connect things in low-frequency read mode. In this case
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// we are generating the unmodulated low frequency carrier.
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// The A/D samples at that same rate and the result is serialized.
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module lo_read(
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input pck0,
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input pck_divclk,
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input [7:0] pck_cnt,
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input [7:0] adc_d,
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input lf_field,
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output ssp_din,
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output ssp_frame,
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output ssp_clk,
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output adc_clk,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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output debug
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);
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reg [7:0] to_arm_shiftreg;
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// this task also runs at pck0 frequency (24MHz) and is used to serialize
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// the ADC output which is then clocked into the ARM SSP.
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// because pck_divclk always transitions when pck_cnt = 0 we use the
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// pck_div counter to sync our other signals off it
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// we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
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always @(posedge pck0)
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begin
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if ((pck_cnt == 8'd7) && !pck_divclk)
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to_arm_shiftreg <= adc_d;
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else
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begin
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to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
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to_arm_shiftreg[0] <= 1'b0;
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end
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end
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// ADC samples on falling edge of adc_clk, data available on the rising edge
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// example of ssp transfer of binary value 1100101
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// start of transfer is indicated by the rise of the ssp_frame signal
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// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
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// the ARM by the falling edge of ssp_clk
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// _______________________________
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// ssp_frame__| |__
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// _______ ___ ___
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// ssp_din __| |_______| |___| |______
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// _ _ _ _ _ _ _ _ _ _
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// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
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// serialized SSP data is gated by pck_divclk to suppress unwanted signal
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assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
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// SSP clock always runs at 24MHz
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assign ssp_clk = pck0;
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// SSP frame is gated by pck_divclk and goes high when pck_cnt=8..15
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assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
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// unused signals tied low
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assign pwr_hi = 1'b0;
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// always on outputs, unused
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assign pwr_oe1 = 1'b0;
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assign pwr_oe2 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = 1'b0;
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// this is the antenna driver signal
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assign pwr_lo = lf_field & pck_divclk;
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// ADC clock out of phase with antenna driver
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assign adc_clk = ~pck_divclk;
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// ADC clock also routed to debug pin
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assign debug = adc_clk;
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endmodule
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