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35 lines
1.2 KiB
Verilog
35 lines
1.2 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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module clk_divider(input clk, input [7:0] divisor, output [7:0] div_cnt, output div_clk);
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reg [7:0] div_cnt_ = 0;
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reg div_clk_;
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assign div_cnt = div_cnt_;
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assign div_clk = div_clk_;
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always @(posedge clk)
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begin
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if(div_cnt == divisor) begin
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div_cnt_ <= 8'd0;
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div_clk_ = !div_clk_;
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end else
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div_cnt_ <= div_cnt_ + 1;
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end
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endmodule
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