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78 lines
2.7 KiB
Verilog
78 lines
2.7 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// There are two modes:
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// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
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// (resp. high) edge/peak is detected, with hysteresis
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// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
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// is detected.
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// That way you can detect two consecutive edges/peaks at the same level (L/H)
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//
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// Output:
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// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
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// - ssp_clk: cross_lo
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`include "lp20khz_1MSa_iir_filter.v"
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`include "lf_edge_detect.v"
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module lo_edge_detect(
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input pck0, input pck_divclk,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk,
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output ssp_frame, input ssp_dout, output ssp_clk,
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input cross_lo,
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output dbg,
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input lf_field,
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input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
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);
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wire tag_modulation = ssp_dout & !lf_field;
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wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
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// No logic, straight through.
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assign pwr_oe1 = 1'b0; // not used in LF mode
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assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
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// when modulating, add another 33 Ohms and 10k Ohms in parallel:
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assign pwr_oe2 = tag_modulation;
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assign pwr_oe4 = tag_modulation;
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assign ssp_clk = cross_lo;
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assign pwr_lo = reader_modulation;
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assign pwr_hi = 1'b0;
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// filter the ADC values
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wire data_rdy;
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wire [7:0] adc_filtered;
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assign adc_clk = pck0;
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lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
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// detect edges
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wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
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wire [7:0] max, min;
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wire edge_state, edge_toggle;
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lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
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max, min,
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high_threshold, highz_threshold, lowz_threshold, low_threshold,
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edge_state, edge_toggle);
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assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
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assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
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endmodule
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