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75 lines
3.1 KiB
C
75 lines
3.1 KiB
C
//-----------------------------------------------------------------------------
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// Jonathan Westhues, April 2006
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// iZsh <izsh at fail0verflow.com>, 2014
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// Routines to load the FPGA image, and then to configure the FPGA's major
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// mode once it is configured.
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//-----------------------------------------------------------------------------
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void FpgaSendCommand(uint16_t cmd, uint16_t v);
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void FpgaWriteConfWord(uint8_t v);
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void FpgaDownloadAndGo(int bitstream_version);
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void FpgaGatherVersion(int bitstream_version, char *dst, int len);
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void FpgaSetupSsc(void);
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void SetupSpi(int mode);
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bool FpgaSetupSscDma(uint8_t *buf, int len);
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void Fpga_print_status();
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#define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
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#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
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void SetAdcMuxFor(uint32_t whichGpio);
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// definitions for multiple FPGA config files support
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#define FPGA_BITSTREAM_MAX 2 // the total number of FPGA bitstreams (configs)
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#define FPGA_BITSTREAM_ERR 0
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#define FPGA_BITSTREAM_LF 1
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#define FPGA_BITSTREAM_HF 2
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// Definitions for the FPGA commands.
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#define FPGA_CMD_SET_CONFREG (1<<12)
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#define FPGA_CMD_SET_DIVISOR (2<<12)
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#define FPGA_CMD_SET_USER_BYTE1 (3<<12)
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// Definitions for the FPGA configuration word.
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// LF
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#define FPGA_MAJOR_MODE_LF_ADC (0<<5)
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#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<5)
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#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<5)
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// HF
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#define FPGA_MAJOR_MODE_HF_READER_TX (0<<5)
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#define FPGA_MAJOR_MODE_HF_READER_RX_XCORR (1<<5)
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#define FPGA_MAJOR_MODE_HF_SIMULATOR (2<<5)
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#define FPGA_MAJOR_MODE_HF_ISO14443A (3<<5)
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#define FPGA_MAJOR_MODE_HF_SNOOP (4<<5)
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// BOTH
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#define FPGA_MAJOR_MODE_OFF (7<<5)
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// Options for LF_ADC
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#define FPGA_LF_ADC_READER_FIELD (1<<0)
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// Options for LF_EDGE_DETECT
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1
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#define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0)
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#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE (1<<1)
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// Options for the HF reader, tx to tag
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#define FPGA_HF_READER_TX_SHALLOW_MOD (1<<0)
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// Options for the HF reader, correlating against rx from tag
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#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)
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#define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1)
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#define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ (1<<2)
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// Options for the HF simulated tag, how to modulate
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#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0) // 0000
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0) // 0001
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#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0) // 0010
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#define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0) // 0100
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#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5 // 0101
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// no 848K
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// Options for ISO14443A
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#define FPGA_HF_ISO14443A_SNIFFER (0<<0)
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#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)
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#define FPGA_HF_ISO14443A_TAGSIM_MOD (2<<0)
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#define FPGA_HF_ISO14443A_READER_LISTEN (3<<0)
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#define FPGA_HF_ISO14443A_READER_MOD (4<<0)
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