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36 lines
1 KiB
Verilog
36 lines
1 KiB
Verilog
//-----------------------------------------------------------------------------
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// For reading TI tags, we need to place the FPGA in pass through mode
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// and pass everything through to the ARM
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//-----------------------------------------------------------------------------
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module lo_passthru(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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// No logic, straight through.
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assign pwr_oe3 = 1'b0;
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assign pwr_oe1 = 1'b1;
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assign pwr_oe2 = 1'b1;
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assign pwr_oe4 = 1'b1;
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assign pwr_lo = 1'b0;
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assign pwr_hi = 1'b0;
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assign adc_clk = 1'b0;
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assign ssp_din = cross_lo;
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assign dbg = cross_lo;
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endmodule
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