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https://github.com/RfidResearchGroup/proxmark3.git
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6658905f18
It is identical to the popular 20081211, with the doob addition (20090301), a linux client, and two additional commands for LF analysis. Let me know if you find issues here!
38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
//-----------------------------------------------------------------------------
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// The way that we connect things in low-frequency simulation mode. In this
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// case just pass everything through to the ARM, which can bit-bang this
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// (because it is so slow).
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module lo_simulate(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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// No logic, straight through.
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assign pwr_oe3 = 1'b0;
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assign pwr_oe1 = ssp_dout;
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assign pwr_oe2 = ssp_dout;
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assign pwr_oe4 = ssp_dout;
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assign ssp_clk = cross_lo;
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assign pwr_lo = 1'b0;
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assign adc_clk = 1'b0;
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assign pwr_hi = 1'b0;
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assign dbg = cross_lo;
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endmodule
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