iceman1001 95d1631bed style		2022-03-23 18:22:03 +01:00
..
tests
clk_divider.v
fpga.ucf
fpga_felica.bit
fpga_felica.v
fpga_hf.bit
fpga_hf.v
fpga_hf_15.bit
fpga_hf_15.v	style	2022-03-23 18:22:03 +01:00
fpga_lf.bit
fpga_lf.v
go.bat
hi_flite.v
hi_get_trace.v
hi_iso14443a.v
hi_reader.v
hi_reader_15.v	style	2022-03-23 18:22:03 +01:00
hi_simulate.v
hi_sniffer.v
lf_edge_detect.v
lo_adc.v
lo_edge_detect.v
lo_passthru.v
lo_read.v
lo_simulate.v
lp20khz_1MSa_iir_filter.v
Makefile
min_max_tracker.v
sim.tcl
testbed_fpga.v
testbed_hi_read_tx.v
testbed_hi_simulate.v
testbed_lo_read.v
testbed_lo_simulate.v
util.v
xst_felica.scr
xst_hf.scr
xst_hf_15.scr
xst_lf.scr