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48 lines
1.5 KiB
Verilog
48 lines
1.5 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// For reading TI tags, we need to place the FPGA in pass through mode
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// and pass everything through to the ARM
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module lo_passthru(
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input pck_divclk,
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input cross_lo,
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input ssp_dout,
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output ssp_din,
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output adc_clk,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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output debug
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);
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// the antenna is modulated when ssp_dout = 1, when 0 the
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// antenna drivers stop modulating and go into listen mode
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assign ssp_din = cross_lo;
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assign adc_clk = 1'b0;
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assign pwr_lo = pck_divclk && ssp_dout;
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assign pwr_hi = 1'b0;
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assign pwr_oe1 = ssp_dout;
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assign pwr_oe2 = ssp_dout;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = ssp_dout;
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assign debug = cross_lo;
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endmodule
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