mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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581 lines
21 KiB
Verilog
581 lines
21 KiB
Verilog
//-----------------------------------------------------------------------------
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// ISO14443-A support for the Proxmark III
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// Gerhard de Koning Gans, April 2008
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//-----------------------------------------------------------------------------
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// constants for the different modes:
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`define SNIFFER 3'b000
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`define TAGSIM_LISTEN 3'b001
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`define TAGSIM_MOD 3'b010
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`define READER_LISTEN 3'b011
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`define READER_MOD 3'b100
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module hi_iso14443a(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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mod_type
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input [2:0] mod_type;
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wire adc_clk = ck_1356meg;
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Reader -> PM3:
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// detecting and shaping the reader's signal. Reader will modulate the carrier by 100% (signal is either on or off). Use a
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// hysteresis (Schmitt Trigger) to avoid false triggers during slowly increasing or decreasing carrier amplitudes
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reg after_hysteresis;
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reg [11:0] has_been_low_for;
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always @(negedge adc_clk)
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begin
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if(adc_d >= 16) after_hysteresis <= 1'b1; // U >= 1,14V -> after_hysteresis = 1
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else if(adc_d < 8) after_hysteresis <= 1'b0; // U < 1,04V -> after_hysteresis = 0
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// Note: was >= 3,53V and <= 1,19V. The new trigger values allow more reliable detection of the first bit
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// (it might not reach 3,53V due to the high time constant of the high pass filter in the analogue RF part).
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// In addition, the new values are more in line with ISO14443-2: "The PICC shall detect the ”End of Pause” after the field exceeds
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// 5% of H_INITIAL and before it exceeds 60% of H_INITIAL." Depending on the signal strength, 60% might well be less than 3,53V.
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// detecting a loss of reader's field (adc_d < 192 for 4096 clock cycles). If this is the case,
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// set the detected reader signal (after_hysteresis) to '1' (unmodulated)
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if(adc_d >= 192)
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begin
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has_been_low_for <= 12'd0;
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end
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else
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begin
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if(has_been_low_for == 12'd4095)
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begin
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has_been_low_for <= 12'd0;
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after_hysteresis <= 1'b1;
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end
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else
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begin
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has_been_low_for <= has_been_low_for + 1;
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Reader -> PM3
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// detect when a reader is active (modulating). We assume that the reader is active, if we see the carrier off for at least 8
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// carrier cycles. We assume that the reader is inactive, if the carrier stayed high for at least 256 carrier cycles.
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reg deep_modulation;
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reg [2:0] deep_counter;
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reg [8:0] saw_deep_modulation;
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always @(negedge adc_clk)
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begin
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if(~(| adc_d[7:0])) // if adc_d == 0 (U <= 0,94V)
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begin
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if(deep_counter == 3'd7) // adc_d == 0 for 8 adc_clk ticks -> deep_modulation (by reader)
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begin
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deep_modulation <= 1'b1;
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saw_deep_modulation <= 8'd0;
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end
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else
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deep_counter <= deep_counter + 1;
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end
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else
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begin
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deep_counter <= 3'd0;
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if(saw_deep_modulation == 8'd255) // adc_d != 0 for 256 adc_clk ticks -> deep_modulation is over, probably waiting for tag's response
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deep_modulation <= 1'b0;
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else
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saw_deep_modulation <= saw_deep_modulation + 1;
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Tag -> PM3
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// filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
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// for noise reduction and edge detection.
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// store 4 previous samples:
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reg [7:0] input_prev_4, input_prev_3, input_prev_2, input_prev_1;
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always @(negedge adc_clk)
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begin
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input_prev_4 <= input_prev_3;
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input_prev_3 <= input_prev_2;
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input_prev_2 <= input_prev_1;
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input_prev_1 <= adc_d;
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end
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// adc_d_filtered = 2*input_prev4 + 1*input_prev3 + 0*input_prev2 - 1*input_prev1 - 2*input
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// = (2*input_prev4 + input_prev3) - (2*input + input_prev1)
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wire [8:0] input_prev_4_times_2 = input_prev_4 << 1;
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wire [8:0] adc_d_times_2 = adc_d << 1;
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wire [9:0] tmp1 = input_prev_4_times_2 + input_prev_3;
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wire [9:0] tmp2 = adc_d_times_2 + input_prev_1;
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// convert intermediate signals to signed and calculate the filter output
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wire signed [10:0] adc_d_filtered = {1'b0, tmp1} - {1'b0, tmp2};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
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// 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
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reg pre_after_hysteresis;
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reg [3:0] reader_falling_edge_time;
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reg [6:0] negedge_cnt;
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always @(negedge adc_clk)
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begin
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// detect a reader signal's falling edge and remember its timing:
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pre_after_hysteresis <= after_hysteresis;
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if (pre_after_hysteresis && ~after_hysteresis)
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begin
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reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
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end
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// adjust internal timer counter if necessary:
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if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_LISTEN) && deep_modulation)
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begin
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if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time.
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begin
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negedge_cnt <= negedge_cnt + 2; // time warp
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end
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else if (reader_falling_edge_time == 4'd0) // reader signal changes right before sampling. Better sample later next time.
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begin
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negedge_cnt <= negedge_cnt; // freeze time
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1; // Continue as usual
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end
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reader_falling_edge_time[3:0] <= 4'd8; // adjust only once per detected edge
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end
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else if (negedge_cnt == 7'd127) // normal operation: count from 0 to 127
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begin
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negedge_cnt <= 0;
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1;
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Tag -> PM3:
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// determine best possible time for starting/resetting the modulation detector.
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reg [3:0] mod_detect_reset_time;
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always @(negedge adc_clk)
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begin
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if (mod_type == `READER_LISTEN)
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// (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by
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// 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks).
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// To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e.
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// at mod_detect_reset_time+4 and mod_detect_reset_time+12 (-4 ticks).
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// 9 + 4 + 3 + 7 - 4 = 19. 19 mod 16 = 3
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begin
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mod_detect_reset_time <= 4'd4;
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end
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else
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if (mod_type == `SNIFFER)
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begin
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// detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
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if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
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// reader signal rising edge detected at negedge_cnt[3:0]. This signal had been delayed
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// 9 ticks by the RF part + 3 ticks by the A/D converter + 1 tick to assign to after_hysteresis.
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// Then the same as above.
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// - 9 - 3 - 1 + 4 + 3 + 7 - 4 = -3
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begin
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mod_detect_reset_time <= negedge_cnt[3:0] - 4'd3;
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Tag -> PM3:
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// modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
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// falling and rising edge (in any order), a modulation is detected.
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reg signed [10:0] rx_mod_falling_edge_max;
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reg signed [10:0] rx_mod_rising_edge_max;
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reg curbit;
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`define EDGE_DETECT_THRESHOLD 5
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always @(negedge adc_clk)
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begin
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if(negedge_cnt[3:0] == mod_detect_reset_time)
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begin
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// detect modulation signal: if modulating, there must have been a falling AND a rising edge
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if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD))
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curbit <= 1'b1; // modulation
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else
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curbit <= 1'b0; // no modulation
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// reset modulation detector
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rx_mod_rising_edge_max <= 0;
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rx_mod_falling_edge_max <= 0;
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end
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else // look for steepest edges (slopes)
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begin
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if (adc_d_filtered > 0)
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begin
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if (adc_d_filtered > rx_mod_falling_edge_max)
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rx_mod_falling_edge_max <= adc_d_filtered;
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end
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else
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begin
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if (adc_d_filtered < rx_mod_rising_edge_max)
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rx_mod_rising_edge_max <= adc_d_filtered;
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Tag+Reader -> PM3
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// sample 4 bits reader data and 4 bits tag data for sniffing
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reg [3:0] reader_data;
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reg [3:0] tag_data;
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always @(negedge adc_clk)
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begin
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if(negedge_cnt[3:0] == 4'd0)
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begin
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reader_data[3:0] <= {reader_data[2:0], after_hysteresis};
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tag_data[3:0] <= {tag_data[2:0], curbit};
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// PM3 -> Reader:
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// a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
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reg [31:0] mod_sig_buf;
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reg [4:0] mod_sig_ptr;
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reg mod_sig;
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always @(negedge adc_clk)
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begin
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if(negedge_cnt[3:0] == 4'd0) // sample data at rising edge of ssp_clk - ssp_dout changes at the falling edge.
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begin
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mod_sig_buf[31:2] <= mod_sig_buf[30:1]; // shift
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if (~ssp_dout && ~mod_sig_buf[1])
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mod_sig_buf[1] <= 1'b0; // delete the correction bit (a single 1 preceded and succeeded by 0)
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else
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mod_sig_buf[1] <= mod_sig_buf[0];
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mod_sig_buf[0] <= ssp_dout; // add new data to the delay line
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mod_sig = mod_sig_buf[mod_sig_ptr]; // the delayed signal.
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// PM3 -> Reader, internal timing:
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// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
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// set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
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// Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
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// a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the
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// transmission stream, causing the required additional delay.
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reg [10:0] fdt_counter;
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reg fdt_indicator, fdt_elapsed;
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reg [3:0] mod_sig_flip;
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reg [3:0] sub_carrier_cnt;
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// we want to achieve a delay of 1172. The RF part already has delayed the reader signals's rising edge
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// by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
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// count to 1172 - 9 - 3 - 32 = 1128
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`define FDT_COUNT 11'd1128
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// The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
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// with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
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// fdt_indicator is assigned to sendbit after at least 1 tick, the transfer to ARM needs minimum 8 ticks. Response from
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// ARM could appear at ssp_dout 8 ticks later.
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// 1128 - 464 - 1 - 8 - 8 = 647
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`define FDT_INDICATOR_COUNT 11'd647
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// Note: worst case, assignment to sendbit takes 15 ticks more, and transfer to ARM needs 7*16 = 112 ticks more.
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// When the ARM's response then appears, the fdt_count is already 647 + 15 + 112 = 774, which still allows the ARM a possible
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// response window of 1128 - 774 = 354 ticks.
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// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
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assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
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always @(negedge adc_clk)
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begin
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if (fdt_reset)
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begin
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fdt_counter <= 11'd0;
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fdt_elapsed <= 1'b0;
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fdt_indicator <= 1'b0;
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end
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else
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begin
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if(fdt_counter == `FDT_COUNT)
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begin
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if(~fdt_elapsed) // just reached fdt.
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begin
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mod_sig_flip <= negedge_cnt[3:0]; // start modulation at this time
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sub_carrier_cnt <= 4'd0; // subcarrier phase in sync with start of modulation
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fdt_elapsed <= 1'b1;
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end
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else
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begin
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sub_carrier_cnt <= sub_carrier_cnt + 1;
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end
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end
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else
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begin
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fdt_counter <= fdt_counter + 1;
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end
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end
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if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// PM3 -> Reader or Tag
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// assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
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// or undelayed when sending to a tag
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reg mod_sig_coil;
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always @(negedge adc_clk)
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begin
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if (mod_type == `TAGSIM_MOD) // need to take care of proper fdt timing
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begin
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if(fdt_counter == `FDT_COUNT)
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begin
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if(fdt_elapsed)
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begin
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if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig;
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end
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else
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begin
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mod_sig_coil <= mod_sig; // just reached fdt. Immediately assign signal to coil
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end
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end
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end
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else // other modes: don't delay
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begin
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mod_sig_coil <= ssp_dout;
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// PM3 -> Reader
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// determine the required delay in the mod_sig_buf (set mod_sig_ptr).
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reg temp_buffer_reset;
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always @(negedge adc_clk)
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begin
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if(fdt_reset)
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begin
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mod_sig_ptr <= 5'd0;
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temp_buffer_reset = 1'b0;
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end
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else
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begin
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if(fdt_counter == `FDT_COUNT && ~fdt_elapsed) // if we just reached fdt
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if(~(| mod_sig_ptr[4:0]))
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mod_sig_ptr <= 5'd8; // ... but didn't buffer a 1 yet, delay next 1 by n*128 ticks.
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else
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temp_buffer_reset = 1'b1; // else no need for further delays.
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if(negedge_cnt[3:0] == 4'd0) // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
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begin
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if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt is reached.
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if (mod_sig_ptr == 5'd31)
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mod_sig_ptr <= 5'd0; // buffer overflow - data loss.
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else
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mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). mod_sig_ptr always points ahead of first 1.
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else if(fdt_elapsed && ~temp_buffer_reset)
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begin
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// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
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// at intervals of 8 * 16 = 128 adc_clk ticks (as defined in ISO14443-3)
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if(ssp_dout)
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temp_buffer_reset = 1'b1;
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if(mod_sig_ptr == 5'd1)
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mod_sig_ptr <= 5'd8; // still nothing received, need to go for the next interval
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else
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mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
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end
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// FPGA -> ARM communication:
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// buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
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reg [7:0] to_arm;
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always @(negedge adc_clk)
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begin
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if (negedge_cnt[5:0] == 6'd63) // fill the buffer
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begin
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if (mod_type == `SNIFFER)
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begin
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if(deep_modulation) // a reader is sending (or there's no field at all)
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begin
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to_arm <= {reader_data[3:0], 4'b0000}; // don't send tag data
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end
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else
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begin
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to_arm <= {reader_data[3:0], tag_data[3:0]};
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end
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end
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else
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begin
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to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]}; // feedback timing information
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end
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end
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if(negedge_cnt[2:0] == 3'b000 && mod_type == `SNIFFER) // shift at double speed
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begin
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// Don't shift if we just loaded new data, obviously.
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if(negedge_cnt[5:0] != 6'd0)
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begin
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to_arm[7:1] <= to_arm[6:0];
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end
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|
end
|
|
|
|
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `SNIFFER)
|
|
begin
|
|
// Don't shift if we just loaded new data, obviously.
|
|
if(negedge_cnt[6:0] != 7'd0)
|
|
begin
|
|
to_arm[7:1] <= to_arm[6:0];
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// FPGA <-> ARM communication:
|
|
// generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
|
|
reg ssp_clk;
|
|
reg ssp_frame;
|
|
|
|
always @(negedge adc_clk)
|
|
begin
|
|
if(mod_type == `SNIFFER)
|
|
// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
|
|
begin
|
|
if(negedge_cnt[2:0] == 3'd0)
|
|
ssp_clk <= 1'b1;
|
|
if(negedge_cnt[2:0] == 3'd4)
|
|
ssp_clk <= 1'b0;
|
|
|
|
if(negedge_cnt[5:0] == 6'd0) // ssp_frame rising edge indicates start of frame
|
|
ssp_frame <= 1'b1;
|
|
if(negedge_cnt[5:0] == 6'd8)
|
|
ssp_frame <= 1'b0;
|
|
end
|
|
else
|
|
// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
|
|
begin
|
|
if(negedge_cnt[3:0] == 4'd0)
|
|
ssp_clk <= 1'b1;
|
|
if(negedge_cnt[3:0] == 4'd8)
|
|
ssp_clk <= 1'b0;
|
|
|
|
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame
|
|
ssp_frame <= 1'b1;
|
|
if(negedge_cnt[6:0] == 7'd23)
|
|
ssp_frame <= 1'b0;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// FPGA -> ARM communication:
|
|
// select the data to be sent to ARM
|
|
reg bit_to_arm;
|
|
reg sendbit;
|
|
|
|
always @(negedge adc_clk)
|
|
begin
|
|
if(negedge_cnt[3:0] == 4'd0)
|
|
begin
|
|
// What do we communicate to the ARM
|
|
if(mod_type == `TAGSIM_LISTEN)
|
|
sendbit = after_hysteresis;
|
|
else if(mod_type == `TAGSIM_MOD)
|
|
/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
|
|
else */
|
|
sendbit = fdt_indicator;
|
|
else if (mod_type == `READER_LISTEN)
|
|
sendbit = curbit;
|
|
else
|
|
sendbit = 1'b0;
|
|
end
|
|
|
|
|
|
if(mod_type == `SNIFFER)
|
|
// send sampled reader and tag data:
|
|
bit_to_arm = to_arm[7];
|
|
else if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
|
|
// send timing information:
|
|
bit_to_arm = to_arm[7];
|
|
else
|
|
// send data or fdt_indicator
|
|
bit_to_arm = sendbit;
|
|
end
|
|
|
|
|
|
|
|
|
|
assign ssp_din = bit_to_arm;
|
|
|
|
// Subcarrier (adc_clk/16, for TAGSIM_MOD only).
|
|
wire sub_carrier;
|
|
assign sub_carrier = ~sub_carrier_cnt[3];
|
|
|
|
// in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
|
|
assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));
|
|
|
|
|
|
// Enable HF antenna drivers:
|
|
assign pwr_oe1 = 1'b0;
|
|
assign pwr_oe3 = 1'b0;
|
|
|
|
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
|
|
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
|
|
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
|
|
assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD);
|
|
|
|
// This is all LF, so doesn't matter.
|
|
assign pwr_oe2 = 1'b0;
|
|
assign pwr_lo = 1'b0;
|
|
|
|
|
|
assign dbg = negedge_cnt[3];
|
|
|
|
endmodule
|