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218 lines
8.4 KiB
Verilog
218 lines
8.4 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The FPGA is responsible for interfacing between the A/D, the coil drivers,
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// and the ARM. In the low-frequency modes it passes the data straight
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// through, so that the ARM gets raw A/D samples over the SSP. In the high-
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// frequency modes, the FPGA might perform some demodulation first, to
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// reduce the amount of data that we must send to the ARM.
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//-----------------------------------------------------------------------------
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module fpga_lf(
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input spck,
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output miso,
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input mosi,
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input ncs,
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input pck0,
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input ck_1356meg,
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input ck_1356megb,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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input [7:0] adc_d,
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output adc_clk,
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output adc_noe,
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output ssp_frame,
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output ssp_din,
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input ssp_dout,
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output ssp_clk,
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input cross_hi,
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input cross_lo,
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output debug,
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output PWR_LO_EN
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);
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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// Receive 16bits of data from ARM here.
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reg [15:0] shift_reg;
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always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
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reg [11:0] conf_word;
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// select module (outputs) based on major mode
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wire [2:0] major_mode = conf_word[8:6];
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// parameter to be passed to modules
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wire lf_field = conf_word[0];
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wire lf_ed_toggle_mode = conf_word[1];
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reg [7:0] lf_ed_threshold;
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wire [7:0] pck_cnt;
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wire pck_divclk;
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reg [7:0] divisor;
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clk_divider div_clk(
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.clk (pck0),
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.divisor (divisor),
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.div_cnt (pck_cnt),
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.div_clk (pck_divclk)
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);
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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// from it, which means that we must make sure that we can do so without
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// glitching, or else we will glitch the transmitted carrier.
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always @(posedge ncs)
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begin
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// 4 bit command
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case (shift_reg[15:12])
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`FPGA_CMD_SET_CONFREG:
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begin
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// 12 bit data
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conf_word <= shift_reg[11:0];
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if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
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begin
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lf_ed_threshold <= 127; // default threshold
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end
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end
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`FPGA_CMD_SET_DIVISOR:
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divisor <= shift_reg[7:0]; // 8bits
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`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
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lf_ed_threshold <= shift_reg[7:0]; // 8 bits
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endcase
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end
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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// 0 -- LF reader (generic)
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lo_read lr(
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.pck0 (pck0),
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.pck_cnt (pck_cnt),
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.pck_divclk (pck_divclk),
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.pwr_lo (lr_pwr_lo),
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.pwr_hi (lr_pwr_hi),
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.pwr_oe1 (lr_pwr_oe1),
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.pwr_oe2 (lr_pwr_oe2),
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.pwr_oe3 (lr_pwr_oe3),
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.pwr_oe4 (lr_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (lr_adc_clk),
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.ssp_frame (lr_ssp_frame),
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.ssp_din (lr_ssp_din),
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.ssp_clk (lr_ssp_clk),
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.debug (lr_debug),
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.lf_field (lf_field)
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);
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// 1 -- LF edge detect (generic)
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lo_edge_detect le(
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.pck0 (pck0),
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.pck_divclk (pck_divclk),
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.pwr_lo (le_pwr_lo),
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.pwr_hi (le_pwr_hi),
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.pwr_oe1 (le_pwr_oe1),
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.pwr_oe2 (le_pwr_oe2),
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.pwr_oe3 (le_pwr_oe3),
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.pwr_oe4 (le_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (le_adc_clk),
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.ssp_frame (le_ssp_frame),
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.ssp_dout (ssp_dout),
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.ssp_clk (le_ssp_clk),
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.cross_lo (cross_lo),
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.debug (le_debug),
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.lf_field (lf_field),
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.lf_ed_toggle_mode (lf_ed_toggle_mode),
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.lf_ed_threshold (lf_ed_threshold)
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);
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// 2 -- LF passthrough
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lo_passthru lp(
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.pck_divclk (pck_divclk),
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.pwr_lo (lp_pwr_lo),
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.pwr_hi (lp_pwr_hi),
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.pwr_oe1 (lp_pwr_oe1),
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.pwr_oe2 (lp_pwr_oe2),
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.pwr_oe3 (lp_pwr_oe3),
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.pwr_oe4 (lp_pwr_oe4),
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.adc_clk (lp_adc_clk),
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.ssp_din (lp_ssp_din),
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.ssp_dout (ssp_dout),
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.cross_lo (cross_lo),
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.debug (lp_debug)
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);
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// 3 -- LF ADC (read/write)
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lo_adc la(
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.pck0 (pck0),
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.pwr_lo (la_pwr_lo ),
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.pwr_hi (la_pwr_hi ),
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.pwr_oe1 (la_pwr_oe1),
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.pwr_oe2 (la_pwr_oe2),
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.pwr_oe3 (la_pwr_oe3),
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.pwr_oe4 (la_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (la_adc_clk),
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.ssp_frame (la_ssp_frame),
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.ssp_din (la_ssp_din),
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.ssp_dout (ssp_dout),
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.ssp_clk (la_ssp_clk),
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.debug (la_debug),
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.divisor (divisor),
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.lf_field (lf_field)
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);
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// Major modes:
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// x0 = LF reader (generic)
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// x1 = LF edge detect (generic)
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// x2 = LF passthrough
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// x3 = LF ADC (read/write)
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// x4 = SPARE
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// x5 = SPARE
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// x6 = SPARE
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// x7 = FPGA_MAJOR_MODE_OFF
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mux8 mux_ssp_clk (.sel(major_mode), .y(ssp_clk ), .x0(lr_ssp_clk ), .x1(le_ssp_clk ), .x2(1'b0 ), .x3(la_ssp_clk ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_ssp_din (.sel(major_mode), .y(ssp_din ), .x0(lr_ssp_din ), .x1(1'b0 ), .x2(lp_ssp_din), .x3(la_ssp_din ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_ssp_frame (.sel(major_mode), .y(ssp_frame), .x0(lr_ssp_frame), .x1(le_ssp_frame), .x2(1'b0 ), .x3(la_ssp_frame), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe1 (.sel(major_mode), .y(pwr_oe1 ), .x0(lr_pwr_oe1 ), .x1(le_pwr_oe1 ), .x2(lp_pwr_oe1), .x3(la_pwr_oe1 ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe2 (.sel(major_mode), .y(pwr_oe2 ), .x0(lr_pwr_oe2 ), .x1(le_pwr_oe2 ), .x2(lp_pwr_oe2), .x3(la_pwr_oe2 ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe3 (.sel(major_mode), .y(pwr_oe3 ), .x0(lr_pwr_oe3 ), .x1(le_pwr_oe3 ), .x2(lp_pwr_oe3), .x3(la_pwr_oe3 ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe4 (.sel(major_mode), .y(pwr_oe4 ), .x0(lr_pwr_oe4 ), .x1(le_pwr_oe4 ), .x2(lp_pwr_oe4), .x3(la_pwr_oe4 ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_lo (.sel(major_mode), .y(pwr_lo ), .x0(lr_pwr_lo ), .x1(le_pwr_lo ), .x2(lp_pwr_lo ), .x3(la_pwr_lo ), .x4(1'b0), .x5(1'b0), .x6(1'b1), .x7(1'b0) );
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mux8 mux_pwr_hi (.sel(major_mode), .y(pwr_hi ), .x0(lr_pwr_hi ), .x1(le_pwr_hi ), .x2(lp_pwr_hi ), .x3(la_pwr_hi ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_adc_clk (.sel(major_mode), .y(adc_clk ), .x0(lr_adc_clk ), .x1(le_adc_clk ), .x2(lp_adc_clk), .x3(la_adc_clk ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_dbg (.sel(major_mode), .y(debug ), .x0(lr_debug ), .x1(le_debug ), .x2(lp_debug ), .x3(la_debug ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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mux8 mux_ant (.sel(major_mode), .y(PWR_LO_EN), .x0(1'b1 ), .x1(1'b1 ), .x2(1'b1 ), .x3(1'b1 ), .x4(1'b0), .x5(1'b0), .x6(1'b0), .x7(1'b0) );
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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endmodule
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