mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-20 23:36:31 +08:00
22 lines
414 B
Verilog
22 lines
414 B
Verilog
//-----------------------------------------------------------------------------
|
|
// Two way MUX.
|
|
//
|
|
// kombi, 2020.05
|
|
//-----------------------------------------------------------------------------
|
|
|
|
module mux2_one(sel, y, x0, x1);
|
|
input [1:0] sel;
|
|
input x0, x1;
|
|
output y;
|
|
reg y;
|
|
|
|
always @(x0 or x1 or sel)
|
|
begin
|
|
case (sel)
|
|
1'b0: y = x1;
|
|
1'b1: y = x0;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|